Free Exhibit to a Document - District Court of Delaware - Delaware

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 1 of 10

IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE PROMOS TECHNOLOGIES, INC., Plaintiff, v. FREESCALE SEMICONDUCTOR, INC., Defendant. ) ) ) ) ) ) ) ) )

C.A. No. 06-788 (JJF)

REVISED TAB 1B TO FREESCALE'S OPENING CLAIM CONSTRUCTION BRIEF Attached is a revised version of Tab 1B to Freescale's Opening Claim Construction Brief (D.I. 85). MORRIS, NICHOLS, ARSHT & TUNNELL LLP

/s/ Mary B. Graham
Mary B. Graham (#2256) James W. Parrett, Jr. (#4292) 1201 N. Market Street P.O. Box 1347 Wilmington, DE 19899-1347 302.658.9200 Attorneys for Freescale Semiconductor, Inc.

OF COUNSEL: David L. Witcoff Kevin P. Ferguson John M. Michalik JONES DAY 77 West Wacker Chicago, IL 60601-1692 312.782.3939 F. Drexel Feeling JONES DAY North Point 901 Lakeside Avenue Cleveland, OH 44114-1190 216.586.3939 Dated: December 13, 2007

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 2 of 10

REVISED TAB 1B (TO FREESCALE'S OPENING CLAIM CONSTRUCTION BRIEF, D.I. 85) ProMOS Technologies, Inc. v. Freescale Semiconductor, Inc., (D. Del.) CA No. 06-788 (JJF) 12-13-2007 Parties' Proposed Claim Constructions for the Chan '709 and '241 Patents Chan Claim Limitation cache memory apparatus* cache memory* Freescale's Constructions A memory chip that is external to the CPU chip. Does not need to be construed because it is not a claim term. A set of pins on the cache memory chip used for the input and output of data over the host data bus. Alternative: [A set of pins] Point of access structure on the cache memory chip package used for the input and output of data over the host data bus. A set of pins on the cache memory chip used for the input and output of data over the system data bus. Alternative: [A set of pins] Point of access structure on the cache memory chip package used for the input and output of data over the system data bus. A cache memory chip having a host port and a system port. A memory chip that is external to the CPU chip. A chip that controls a cache chip. ProMOS's Constructions Does not need construction. Small block of high speed memory associated with a computer processor/ microprocessor (CPU). Interface between a cache memory and a host processor or host data bus.

host port*

system port*

Interface between a cache memory and a system memory or system data bus.

dual port cache memory*

A cache memory that has two interfaces.

cache controller

controller

A chip that controls a cache chip.

Circuitry that controls the transfer of data or other information to and from cache memory. Does not need construction.

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 3 of 10

Chan Claim Limitation first port*

Freescale's Constructions Set of pins on cache controller chip used for the input and output of address information over the host address bus. Alternative: [Set of Pins] Point of access structure on cache controller chip package used for the input and output of address information over the host address bus. Set of pins on cache controller chip used for the input and output of address information over the system address bus. Alternative: [Set of pins] Point of access structure on cache controller chip package used for the input and output of address information over the system address bus. A single chip central processing unit (CPU) A single chip central processing unit (CPU). A single chip central processing unit (CPU). Does not need to be construed because it is not a claim term but means: a set of conductors used to transfer data between devices. A set of conductors connected to the address terminal pins of a CPU chip used to transfer memory addresses from the CPU to other components of a computer system. A set of conductors connected to the data terminal pins of the CPU used to transfer data to and from the CPU and other components of a computer system.

ProMOS's Constructions Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a port connected to the host address bus.

second port*

Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a port connected to the system address bus.

host

host microprocessor host processor bus*

CPU associated with one or more cache memories. Does not need construction. CPU associated with one or more cache memories. CPU associated with one or more cache memories. Line or set of lines used to transfer data or other information.

host address bus

host data bus

Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a bus for providing a host address. Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a bus for providing a host address.

-2-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 4 of 10

Chan Claim Limitation buffering

Freescale's Constructions Using a storage element (e.g., memory write register) as an intermediary device to hold data temporarily while the data is waiting to be transferred from one external device (e.g., the CPU) to another external device (e.g., system memory) because of differences in rates of data flow or time of occurrence of events. Indefinite ­ no corresponding structure disclosed in the specification.

ProMOS's Constructions Storing data temporarily to compensate for differences in rates of data flow, time of occurrence of events, or amounts of data that can be handled by the devices or processes involved in the transfer or use of data.

means for identifying ones of the fetched data held in said memory update register as not corresponding to ones of the second data held in said write back register for write back to said system port

means for identifying ones of the fetched data held in said memory update register as not corresponding to ones of the write back data held in said write back register for write back to said system port

Indefinite ­ no corresponding structure disclosed in the specification.

means for masking the providing of selected ones of said words of the fetched data to said random access memory

Indefinite ­ no corresponding structure disclosed in the specification.

Means plus function. Function: identifying ones of the fetched data held in said memory update register as not corresponding to ones of the write back data held in said write back. register for write back to said system port. Corresponding Structure: the valid bits associated with the memory update register set 116. Means plus function. Function: identifying ones of the fetched data held in said memory update register as not corresponding to ones of the write back data held in said write back register for write back to said system port. Corresponding Structure: the valid bits associated with the memory update register set 116. Means plus function. Function: masking the providing of selected ones of said words of the fetched data to said random access memory. Corresponding Structure: the mask bits associated with the memory update register set 116.

-3-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 5 of 10

Chan Claim Limitation

Freescale's Constructions

ProMOS's Constructions Means plus function. Function: masking writing of selected words of data into said random access memory. Corresponding Structure: the mask bits associated with the memory update register set 116. Means plus function. Function: disabling said dual port cache memory during a local bus access cycle. Corresponding Structure: circuitry within the Controller 70 that evaluates host address and control signals and determines when a host bus cycle is not passed on to the system bus and does not cause a cache hit/miss determination. This includes the circuitry within Local Processor Interface Unit 220 and Control Register Interface Unit 224. Operation of the circuitry is described at 42:5843:42, with reference to Fig. 37 and 38 and in Table VI at 39:2735. Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. To the extent that Freescale is suggesting that the term "first control sequencer" needs to be construed, and to the extent the Court decides to construe the term, it means: a first machine which puts items of information into a particular order. (Not means plus function).

means for masking writing Indefinite ­ no corresponding of selected words of data structure disclosed in the into said random access specification. memory

means for disabling said dual port cache memory during a local bus access cycle

Indefinite ­ no corresponding structure disclosed in the specification.

first control sequencer for controlling addressing and data signals on said host address bus and on said host data bus

Indefinite ­ no corresponding structure disclosed in the specification.

operations at said system port to be decoupled from said random access memory operably decoupled

Indefinite.

Indefinite.

Does not need construction.

-4-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 6 of 10

Chan Claim Limitation register*

Freescale's Constructions Does not need to be construed because it is not a claim term but means: a set of bits of high-speed memory within an electronic device, used to hold data for a particular purpose. Indefinite.

ProMOS's Constructions Circuitry capable of retaining data or other information, such as address information

host input register

system input register system output register

Indefinite. Indefinite.

first input register

Indefinite.

first output register

Indefinite.

second input register

Indefinite.

Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: (in claim 10) a register connected to the host port (in claim 15) a register coupled to the addressable memory storage and the host data bus. Does not need construction. Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a register connected to the system port. Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a register for selectively writing input data to the addressable storage. Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a register for selectively furnishing output data to the system port. Does not need construction; meaning is clear from the claim language. To the extent the Court decides to construe the term, it means: a register for providing second input data to the addressable storage.

-5-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 7 of 10

Chan Claim Limitation a data path between said host data bus and said system data bus is operably decoupled by buffering and selective provision of data to and from said cache storage locations by said plurality of registers* so as to allow concurrent transfer of data to and from said dual port cache memory system memory

Freescale's Constructions The claim phrase "operably decoupled by buffering and selective provision of data to and from said cache storage locations by said plurality of registers" is indefinite.

ProMOS's Constructions Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. See ProMOS's position on "operably decoupled", "buffering," "selective provision", "plurality of registers" and "to allow", above. The term "data path" is clear on its face and does not require construction.

Main memory of a computer system that is external to the CPU chip Whenever the first input data is provided to the RAM, the first output data must be provided to the system port.

first input data being provided to said random access memory from said memory write register at the same time that the first output data is provided by said write back register to said system port wherein the input data is provided to said random access memory from said memory write register at the same time that the output data is provided by said write back register to said system port said input data being provided to said addressable storage from said first input register at the same time that said output data is provided by said first output register to said system port

Whenever input data is provided to the RAM, output data must be provided to the system port.

Whenever the input data is provided to the addressable storage, the output data must be provided to the system port.

Main memory of a computer, relatively larger and slower than cache memory. Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. To the extent Freescale is suggesting that the terms "being provided" and "at the same time" need to be construed, these terms are clear on their face. Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. To the extent Freescale is suggesting that the terms "is provided" and "at the same time" need to be construed, these terms are clear on their face. Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. To the extent Freescale is suggesting that the terms "being provided" and "at the same time" need to be construed, these terms are clear on their face.

-6-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 8 of 10

Chan Claim Limitation said second input data being provided to said addressable storage from said second input register at the same time that said second output data is provided by said second output register to said system port selectively providing input data received from said host port to one of said random access memory, said system port, and said random access memory and said system port

Freescale's Constructions Whenever the second input data is provided to the RAM, the second output data must be provided to the system port.

ProMOS's Constructions Does not need construction. It is not clear which term of this claim element Freescale wishes to construe. To the extent Freescale is suggesting that the terms "being provided" and "at the same time" need to be construed, these terms are clear on their face. Does not need construction. It is not clear which term Freescale wishes to construe. See ProMOS's construction of "host port" and "system port" and ProMOS's position on "selectively providing" and "random access memory."

selectively providing

Providing input data received from the host port to: said random access memory and not to said system port under one set of conditions, said system port and not to said random access memory under a second set of conditions, and said random access memory and said system port under a third set of conditions. Providing data held in a register depending on certain conditions and never providing data held depending on other conditions.

selective provision

selectively providing the first data to one of said random access memory, said system port, and said random access memory and said system port

selectively furnishing first output data to said system port

Does not need construction. To the extent the Court decides to construe the term anyway, it means: providing on a selective basis. Providing data held in a register Does not need construction. To depending on certain conditions and the extent the Court decides to never providing data held depending construe the term anyway, it on other conditions. means: provision on a selective basis. Providing the first data to: said Does not need construction. It is random access memory and not to not clear which term Freescale said system port under one set of wishes to construe. See ProMOS's conditions, said system port and not construction of "system port" to said random access memory above, and ProMOS's position on under a second set of conditions, "selectively providing" and and said random access memory and "random access memory above. said system port under a third set of conditions. Furnishing first output data received Does not need construction. It is from the RAM and held in the write not clear which term Freescale back register to said system port wishes to construe. See ProMOS's depending on certain conditions and construction of "system port" never furnishing first output data above and ProMOS's position on depending on other conditions. "selectively furnishing" below.

-7-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 9 of 10

Chan Claim Limitation selectively providing second input data to said random access memory

Freescale's Constructions Providing second input data received from the system port and held in the memory update register to said random access memory depending on certain conditions and never providing second input data depending on other conditions. Furnishing data received from the RAM and held in the write back register to said system port depending on certain conditions and never furnishing data received from the RAM depending on other conditions. Providing data buffered in the memory write register from the host port to: -said random access memory and not to said system port under one set of conditions, -said system port via said bypass path and not to said random access memory under a second set of conditions, and -said random access memory and said system port via said bypass path under a third set of conditions. Providing system fetch data received from the system port and held in the memory update register to said random access memory depending on certain conditions and never providing system fetch data depending on other conditions. Writing data held in a register depending on certain conditions and never writing data held depending on other conditions. Furnishing data held in a register depending on certain conditions and never furnishing data held depending on other conditions.

ProMOS's Constructions Does not need construction. It is not clear which term Freescale wishes to construe. See ProMOS's position on "selectively writing" below and its position on "random access memory." Does not need construction. It is not clear which term Freescale wishes to construe. See ProMOS's construction of "system port" above and ProMOS's position on "selectively furnishing" below. Does not need construction. It is not clear which term Freescale wishes to construe. See ProMOS's construction of "system port" and its position on "selectively providing" and "random access memory."

selectively furnishing write back data to said system port

selectively providing memory write data to one of said random access memory, said system port via said bypass path, and said random access memory and said system port via said bypass path

selectively providing system fetch data to said random access memory

Does not need construction. It is not clear which term Freescale wishes to construe. See ProMOS's position on "selectively providing" and "random access memory."

selectively writing

selectively furnishing

Does not need construction. To the extent the Court decides to construe the term anyway, it means: writing on a selective basis. Does not need construction. To the extent the Court decides to construe anyway, it means: furnishing on a selective basis.

1333515

-8-

Case 1:06-cv-00788-JJF

Document 97

Filed 12/13/2007

Page 10 of 10

CERTIFICATE OF SERVICE I hereby certify that on December 13, 2007, I caused the foregoing to be electronically filed with the Clerk of the Court using CM/ECF which will send electronic notification of such filing to the following: John G. Day, Esquire Steven J. Balick, Esquire ASHBY & GEDDES

Additionally, I hereby certify that true and correct copies of the foregoing were caused to be served on December 13, 2007 upon the following individuals in the manner indicated: BY E-MAIL John G. Day, Esquire Steven J. Balick, Esquire ASHBY & GEDDES [email protected] [email protected] Sten A. Jensen, Esquire HOGAN & HARTSON LLP [email protected] BY E-MAIL Steven J. Routh, Esquire HOGAN & HARTSON LLP [email protected] William H. Wright, Esquire HOGAN & HARTSON LLP [email protected] William C. Gooding, Esquire GOODING & CRITTENDEN, L.L.P. [email protected]

/s/ Mary B. Graham
Mary B. Graham (#2256)