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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE PROMOS TECHNOLOGIES, INC., Plaintiff, v. FREESCALE SEMICONDUCTOR, INC., Defendant. ) ) ) ) ) ) ) ) ) )

C.A. No. 06-788 (JJF)

FREESCALE'S OPENING CLAIM CONSTRUCTION BRIEF MORRIS, NICHOLS, ARSHT & TUNNELL LLP Mary B. Graham (#2256) James W. Parrett, Jr. (#4292) 1201 N. Market Street P.O. Box 1347 Wilmington, DE 19899-1347 302.658.9200 OF COUNSEL: David L. Witcoff Kevin P. Ferguson John M. Michalik JONES DAY 77 West Wacker Chicago, IL 60601-1692 312.782.3939 F. Drexel Feeling JONES DAY North Point 901 Lakeside Avenue Cleveland, OH 44114-1190 216.586.3939 Dated: November 6, 2007 Attorneys for Freescale Semiconductor, Inc.

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TABLE OF CONTENTS Page TABLE OF AUTHORITIES INTRODUCTION THE FORTIN PATENT I. STATEMENT OF FACTS A. B. II. Chip Fabrication Technology Fortin's Specific PVD Process ii 1 2 2 2 6 9 and "chemical vapor 9 14 15 17 17 17 19 22 22 24 25 25

FORTIN CLAIM CONSTRUCTIONS A. B. C. "physical vapor deposition" "sputtering" "rounding" deposition"

THE CHAN PATENTS I. CHAN TECHNOLOGY A. B. II. Cache Memory Internal vs. External Cache

THE CHAN PATENTS A. B. Overview of the `709 Patent Overview of the `241 Patent

III.

THE CHAN INTRINSIC RECORD A. The Prosecution History Demonstrates That The Chan Patents Are Directed To An External Cache 1. The Specification Of The `709 And `241 Patents Was Copied From MOSEL's Product Literature Describing An External Cache

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2.

The `709 Claims Were Amended Four Times And Incorporated Limitations From The MOSEL Cache Chip Each Time The `241 Claims Were Amended Five Times And Incorporated Limitations From The MOSEL Chips Each During Prosecution, The `709 And `241 Claims Were Limited To An External Cache Chip

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3.

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4. B.

The Specification Also Demonstrates That The Claims Of The Chan Patents Are Directed To An External Cache 1. The Specification Of The `709 And `241 Patents Consistently Refers To A Cache External To The CPU As The Invention The Chan Specification Disclaimed An Internal Cache

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2. C.

Construing The Chan Patents To Be Limited To An External Cache Is Not Impermissibly Importing A Limitation From The Specification

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IV.

CHAN CLAIM CONSTRUCTIONS A. "cache memory apparatus" / "cache memory" - `709 claims 1, 13, 17, 22 and `241 claims 1, 15, 16 1. Preamble Claim Terms Should Be Construed Where, As In This Case, They Give Meaning To The Claimed Invention The Chan Specification Disclaimed A Cache Memory That Is Internal To A Processor Chip Chan Described The Invention As Being Directed To A Memory Chip That Is External To The CPU Chip An Object Of The Invention Cannot Be Achieved Unless The "Cache Memory Apparatus" Is Construed As An External Cache MOSEL's Description Of Chan's Patented Product Illustrates That The Cache Memory Is A Chip That Is External To The Processor

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2. 3.

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4.

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5.

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B.

"host port" and "system port" - `709 claims 1, 13, 17, 22 and `241 claims 1, 10, 16 1. The Specification Is Clear That The Host Port And System Port Are Pins On The Cache Memory Chip

39 40 41 42 43 43 44 45 47

C. D. E. F. G. H. I. J.

"dual port cache memory" - `241 claims 1, 15 and 16 "cache controller" / "controller" - `241 claims 1, 15 and 16 "first port" and "second port" - `241 claims 1 and 16 "host processor" / "host" / "host microprocessor" - `241 claims 1, 10, 15, 16 "host address bus" and "host data bus" "buffering" - `709 claims 1, 13 & 22 and `241 claim 1 "selectively providing" - `709 Claims 1, 13, 17 and 22 "selectively providing the first data to one of said random access memory, said system port, and said random access memory and said system port" - `709 Claim 1 "at the same time" - `709 Claim 13 and 22 Means-Plus-Function Claim Terms 1. Non-Presumptive Terms Means-Plus-Function Claim

48 49 49 50

K. L.

M.

Indefinite Phrase: "operations at said system port to be decoupled from said random access memory" - (`709 claims 17 and 22) Indefinite Term: "operably decoupled" (`241 claim 1) Indefinite Register Terms: Host Input Register (Chan `241: 10, 15), First Input Register (Chan `241: 16), System Output Register (Chan `241: 10), First Output Register (Chan `241: 16), Second Output Register (Chan `241: 16), System Input Register (Chan `241: 10, 15), Second Input Register (Chan `241: 16) Indefinite Phrase: "buffering and selective provision of data to and from said cache storage locations by said plurality of registers" (`241 claim 1)

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N. O.

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P.

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Q.

"system memory" - `241 claims 1, 15 and 16

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TABLE OF AUTHORITIES Page(s) CASES ACTV, Inc. v. Walt Disney Co., 346 F.3d 1082 (Fed. Cir. 2003) Allen Eng'g Corp. v. Bartell Indus., Inc., 299 F.3d 1336 (Fed. Cir. 2002) Alloc, Inc. v. ITC, 342 F.3d 1361 (Fed. Cir. 2003) Amgen Inc. v. Hoechst Marion Roussel, 314 F.3d 1313 (Fed. Cir. 2003) Applied Materials, Inc. v. Advanced Semiconductor Materials Am., Inc., 98 F.3d 1563 (Fed. Cir. 1996) Applied Science & Tech., Inc. v. Advanced Energy Indus., Inc., 204 F. Supp. 2d 712 (D. Del. 2002) Atmel Corp. v. Info. Storage Devices, 198 F.3d 1374 (Fed. Cir. 1999) Bell Commc'n Research, Inc. v. Vitalink Comm. Corp., 55 F.3d 615 (Fed. Cir. 2007) Biomedino, LLC v. Waters Techs. Corp., 490 F.3d 946 (Fed. Cir. 2007) Chimie v. PPG Indus., Inc., 402 F.3d 1371 (Fed. Cir. 2005) Chuminatta Concrete Concepts, Inc. v. Cardinal Indus., Inc., 145 F.3d 1303 (Fed. Cir. 1998) Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293 (Fed. Cir. 2005) Cultor Corp. v. A.E. Staley Mfg. Co., 224 F.3d 1328 (Fed. Cir. 2000) Curtiss-Wright Flow Control Corp. v. Velan, Inc., 438 F.3d 1374 (Fed. Cir. 2006) 11 15 31-32, 37 16, 51, 55 34-35 13 15 34-35 50 9, 25, 29, 31 50 37 32 37

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Default Proof Credit Card Sys. v. Home Depot U.S.A., 412 F.3d 1291 (Fed. Cir. 2005) Dresser Indus., Inc. v. United States, 432 F.2d 787 (Ct. Cl.1970) Envirotech Corp. v. Al George, Inc., 730 F. 2d 753 (Fed. Cir. 1984) Honeywell Int'l, Inc. v. ITC, 341 F.3d 1332 (Fed. Cir. 2003) Intel Corp. v. Broadcom Corp., No. 00-796-SLR, 2003 U.S. Dist. LEXIS 2372 (D. Del. Feb. 13, 2003) Karlin Tech. Inc. v. Surgical Dynamics, Inc., 177 F.3d 968 (Fed. Cir. 1999) Mackay Radio & Tel. Co., Inc. v. Radio Corp. of Am., 306 U.S. 86 (1939) Markman v. Westview Instruments, Inc., 52 F.3d 967 (Fed. Cir. 1995), aff'd 517 U.S. 370 (1996) Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340 (Fed. Cir. 2004) MicroStrategy, Inc. v. Bus. Objects SA, 429 F.3d 1344 (Fed. Cir. 2005) Nystrom v. TREX Co., 424 F.3d 1136 (Fed. Cir. 2005) Oak Tech., Inc. v. Int'l Trade Comm'n, 248 F.3d 1316 (Fed. Cir. 2001) Personalized Media Commc'ns, LLC v. Int'l Trade Comm'n, 161 F.3d 696 (Fed. Cir. 1998) Phillips v. AWH Corp, 415 F.3d 1303 (Fed. Cir. 2005) Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298 (Fed. Cir. 1999) Power Integrations, Inc. v. Fairchild Semiconductor Int'l, Inc., 422 F. Supp. 2d 446 (D. Del. 2006)

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Prism Techs. LLC v. Verisign, Inc., 2007 WL 988564 (D. Del. Apr. 2, 2007) Rockwell Int'l Corp. v. United States, 147 F.3d 1358 (Fed. Cir. 1998) SciMed Life Sys., Inc. v. Advanced Cardiovascular Sys., Inc., 242 F.3d 1337 (Fed. Cir. 2001) Seachange Int'l, Inc. v. C-COR Inc., 413 F.3d 1361 (Fed. Cir. 2005) Spectrum Int'l, Inc. v. Sterilite Corp., 164 F.3d 1372 (Fed. Cir. 1998) Tap Pharm. Prods., Inc. v. Owl Pharms., 419 F.3d 1346 (Fed. Cir. 2005) Texas Instruments Inc. v. United States Int'l Trade Comm'n, 988 F.2d 1165 (Fed. Cir. 1993) Turbocare Div. Of Demag Delaval Turbomachinery Corp. v. Gen. Elec. Co., 264 F.3d 1111 (Fed. Cir. 2001) Twin Disc, Inc., v. United States, 231 U.S.P.Q. 417 (Ct. Cl. 1986) STATUTES 35 U.S.C. § 112 ¶ 1 35 U.S.C. § 112 ¶ 2 35 U.S.C. § 112, ¶ 6 35 U.S.C. § 132

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INTRODUCTION Freescale Semiconductor, Inc. ("Freescale") is a global leader in the design and manufacture of semiconductor products for the automotive, consumer, industrial, networking and wireless markets. After more than 50 years as Motorola's in-house semiconductor products sector, Freescale was spun off in July 2004. Based in Austin, Texas, Freescale has operations for design, research and development, manufacturing and sales in more than 30 countries. Its semiconductor components are used in well-known consumer products, such as Motorola cell phones, Sony electronics, Whirlpool appliances, Life Fitness cardiovascular and strength training equipment, Cisco routers, Bose Acoustic Wave radios, and many motor vehicles. Freescale and its engineers have received important recognition for innovation. For example, the U.S. Commerce Department awarded Motorola (then including Freescale) the 2004 National Medal of Technology for "75 years of technological achievement and leadership in the development of innovative electronic solutions, which have enabled portable and mobile communications to become the standard across society." The U.S. Patent Office has granted Motorola and Freescale over 5,000 patents relating to semiconductor technology. In the early 1990's, Motorola (later Freescale) was a leading manufacturer of DRAM (i.e., the key kind of memory for computers). Motorola applied for and received numerous DRAM patents on its groundbreaking innovations. The early 1990's marked an increase in competition from foreign DRAM manufacturers who, instead of developing their own technologies, copied technology of industry leaders such as Freescale, and then undercut U.S. DRAM manufacturers' prices. In response, Freescale stopped making memory products and instead focused on semiconductor products. Nevertheless, because Freescale had developed a valuable DRAM patent portfolio, nearly all of the top worldwide DRAM manufacturers took a license to use Freescale's patented DRAM technology. -1-

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ProMOS, however, refused to license the Freescale technology it was using. After years of fruitless negotiations where ProMOS kept stalling, Freescale filed a patent infringement lawsuit against ProMOS in the Eastern District of Texas. ProMOS filed this suit in retaliation. ProMOS is asserting three patents against Freescale: the Fortin patent directed to part of a process for manufacturing semiconductor chips, and two Chan patents directed to cache memory products. ProMOS admittedly does not use these patents. Neither does Freescale. To try to reach Freescale's different technology, however, ProMOS is attempting to stretch the meaning of the claims well beyond the meanings used and disclosed by Fortin and Chan. THE FORTIN PATENT I. STATEMENT OF FACTS A. Chip Fabrication Technology

Semiconductor "chips" are used in electronics to quickly and compactly perform numerous electrical operations. Using well-known fabrication processes, chips are made by Freescale and other chip manufacturers by placing a large number of tiny components, such as transistors and capacitors, on a single semiconductor wafer. Thin layers of metal are deposited to form the connections among those components to create individual electrical circuits within the chip. These metal layers are separated by electrically insulating layers. For a chip to function as desired, electrically conductive paths (sometimes called "plugs") must connect the metal layers through the intervening insulating layers to form a complete, functional "integrated circuit." One way that plugs are made is to first create holes (also called "contact openings" or sometimes "vias") in the insulating layer and then to fill the holes with a conductive material before depositing the next metal layer. conductive material) widely used to fill contact openings. The four basic, well-known steps involved in making a tungsten plug for an integrated Tungsten is a metal (thus a

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circuit include: (i) forming an insulating layer over a metal layer, (ii) creating a contact opening in the insulating layer to expose the metal layer underneath the insulating layer, (iii) forming a "barrier" layer (typically made of titanium nitride ("TiN") or a combination of titanium ("Ti") followed by TiN) over the insulating layer that extends into the contact opening, and (iv) filling the contact opening with tungsten. The tungsten plug forms a conductive path connecting the metal layer underneath the insulating layer to the metal layer then added on top of the insulating layer.1 The TiN barrier layer (formed in step (iii) above) is a "barrier" in the sense that, although electrically conductive, it protects the surrounding insulating layer (or Ti layer where the barrier layer consists of both Ti and TiN) from chemically reacting with the subsequently deposited tungsten. (Chang, et al., Effects of Barrier­Metal Schemes of Tungsten Plugs and Blanket Film Deposition, at 4738 (Ex. B); Herner, et al., "Volcano" Reactions in Oxide Vias Between Tungsten CVD and Bias Sputtered TiN/Ti Films, at 1982 (Ex. C)). Freescale, its predecessor Motorola, and other chip manufacturers have been following these basic steps to fabricate chips for decades. The Fortin patent claims certain alleged improvements in one way of carrying out these common steps ­ a way that the accused processes do not use. Of particular focus in this litigation is the formation of the barrier layers of TiN. The two main techniques for doing so are physical vapor deposition ("PVD") and chemical vapor

1

The background section of Fortin describes these well-known steps: step 1 deposits a "dielectric" layer (i.e., nonconductive or insulating layer) over a metal or silicon layer; in step 2, "A via is etched in the dielectric" (i.e., a hole is made in the insulating layer); step 3 deposits a titanium layer and then a TiN layer; in step 4, a tungsten layer is deposited to complete the formation of the plug, after which another metal layer is deposited (Ex. A at 1:25­39). The exhibits cited in this brief are in appendices of exhibits filed herewith in separate volumes for Fortin (lettered exhibits) and Chan (numbered exhibits). At TAB 1 attached to this brief are claim charts of the terms in dispute; TAB 2 provides a grouping of the similar Chan terms in dispute.

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deposition ("CVD"). (Plummer, et al., Silicon VLSI Technology: Fundamentals, Practice and Modeling (2000), at 511 (Ex. D)). PVD and CVD are well known and have been used for decades to deposit materials in a variety of applications, including layers during chip fabrication. (Wang, et al., Enhanced Metalorganic Chemical Vapor Deposition Titanium Nitride Film Fabricated Using Tetrakis-Demethylamino-Titanium for Barrier Metal Application in Sub-HalfMicron Technology, at 4274 (Ex. E)). "In each case, the silicon wafer is placed in a deposition chamber, and the constituents of the [layer to be deposited] are delivered through the gas phase to the surface of the substrate where they form the [layer]" (Ex. D, Plummer at 511). In other words, both processes, using a vapor, deposit material to build up a layer. The mechanisms of action, however, differ in the two processes. As their names suggest, PVD involves physical mechanisms while CVD involves chemical reactions: "In the case of CVD, reactant gases are introduced into the deposition chamber, and chemical reactions between the reactant gases [taking place] on the substrate surface are used to produce the [layer]. In the case of PVD, physical methods are used to produce the constituent atoms which pass through a low-pressure gas phase [vapor] and then condense2 on the substrate." (Id.; see also Wolf, et al., Silicon Processing for the ULSI Era (2000), at 149 (CVD), 434 (PVD) (Ex. F)). A common example of PVD is "sputtering," which involves a particular way of converting into a vapor the material to be deposited, i.e. through bombarding a "target" surface of the material, thereby dislodging atoms from the surface of the target to form the vapor which then condenses on the substrate (Ex. F, Wolf at 434). For example, sputtering is often used to form a vapor of TiN from a solid target (Id. at 438). In the fabrication of barrier layers using CVD, a common starting chemical material is
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Condensation is a physical mechanism also.

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TiCl4/NH3 (used by prior art cited in the prosecution history) or TDMAT (a material containing titanium, which the accused processes use). One product of the chemical reaction of these starting materials during CVD is TiN, which accumulates on the insulating layer surface. CVD techniques are often followed by a N2/H2 treatment (called a "plasma" treatment) to remove contaminants in the barrier layer leftover from the TiCl4/NH3 or TDMAT starting material. This plasma treatment improves the conductivity and reduces the thickness of the deposited barrier layer by removing the contaminants. In addition to the steps outlined above, it is common to include a "pre-clean" step, usually involving a plasma etch, to clean the contact opening prior to forming the barrier layer (i.e., between steps ii and iii, above). After forming the barrier layer, it is also common to "anneal" (or heat) the barrier layer (between steps iii and iv, above) in a nitrogen atmosphere to improve barrier layer durability as well as adhesion of the tungsten plug to the barrier layer. PVD techniques for forming TiN barrier layers have been popular since the early 1990's because of their relatively low cost and ease of production. As chips have become smaller and smaller, however, manufacturers have faced problems with TiN barrier layers formed by PVD. (Ex. E, Wang at 4274; Ex. B, Chang at 4738). These problems stem from the inconsistent, nonuniform deposition of the TiN barrier layer at different points within the contact openings, also known as poor "step coverage," which lead to weak or failing barrier layers.3 (Ex. E, Wang at 4274; Ex. B, Chang at 4738; Ex. C, Herner at 1982). Chip manufacturers have generally addressed poor step coverage in contact openings in

3

Step coverage refers to the quality and uniformity of barrier layer formation within the contact opening. It generally decreases as contact holes get deeper while the openings at the top of the hole get narrower, such that poor, or inadequately weak, barrier layers form on the sidewalls or bottom corners of a contact hole.

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one of two ways: (1) improving step coverage and barrier layer durability for existing PVD techniques (see Ex. C, Herner at 1982), as Fortin sought4; or (2) using CVD instead of PVD, as in Freescale's accused HiP7 and HiP8 processes. CVD provides much better step coverage in the contact opening than PVD. (Ex. E, Wang at 4274; Ex. B, Chang at 4738). B. Fortin's Specific PVD Process

Vincent Fortin filed his patent application in this well-developed field on June 13, 2001. Fortin discloses and claims a process for fabricating tungsten plugs using TiN barrier layers of a certain thinness formed by PVD (`267 patent see, e.g., the abstract and claim 1 (Ex. A)). There can be no question that Fortin's invention is limited to the formation of TiN layers by PVD. Indeed, the Fortin patent is titled "Formation of Tungsten-Based Interconnect Using Physically Vapor Deposited Titanium Nitride Layer" and the patent's specification begins: "The present invention relates to physical vapor deposition of titanium nitride" (Ex. A at 1:8­9) (emphasis added). Describing the prior art, Fortin acknowledged that it was known to form TiN barrier layers by CVD: "Titanium nitride layer 150 can be deposited by a number of techniques, including sputtering and chemical vapor deposition (CVD)" (Ex. A at 1:40-42). But he claimed as his invention forming TiN barrier layers only by PVD techniques. Every claim of the patent specifically limits the TiN deposition step to PVD, with certain claims directed to the particular PVD process of sputtering5 (Ex. A).6

4 5

6

Fortin referred to the problem as the presence of "volcanoes" or "voids." This should not be confused with the formation of the tungsten layer by CVD, which the patent also claims. It is the use of PVD for the TiN layer that presents the key issue for claim construction, although Freescale and ProMOS agree that CVD also requires construction. A representative claim of Fortin is claim 1: "A fabrication method comprising: providing a structure with an opening that extends partway through the structure, the opening having a parametrical top edge that extends along an exterior surface of the structure; rounding the top edge of the opening; forming a titanium nitride layer over the structure by physical vapor (Continued . . .) -6-

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That Fortin is limited to forming the TiN layer by PVD was explicitly reaffirmed during prosecution. The Examiner initially rejected most of Fortin's claims over U.S. Pat. No.

5,420,072 to Fiordalice ("Fiordalice"), which discloses fabrication of TiN barrier layers as thin as those claimed by Fortin (using TiCl4/NH3 as the starting material). (Ex. G, at 3-7). In response, Fortin argued successfully that his invention was patentable because Fiordalice discloses forming a TiN layer by CVD, whereas his invention forms the TiN layer by PVD: "Fiordalice discloses that layers 22 and 24 are formed by chemical vapor deposition ("CVD"), not physical vapor deposition ("PVD") (Ex. H at 9; see also id. at 9-10) ("Since Fiordalice discloses that titanium nitride layers 22 and 24 are formed by CVD, . . . Fiordalice cited by the Examiner in regard to deposition of the titanium nitride layer, does not disclose the limitation of [Fortin] Claim 1 that the titanium nitride layer be formed by PVD to a thickness of less than 30 nm.") (original emphasis). To drive home the point, Fortin emphasized, "In any event, CVD is not PVD or a type of PVD." (Ex. H at 9) (emphasis in original). As part of his argument, Fortin confirmed his ordinary use of the terms (Ex. H at 9) (emphasis in original). He characterized PVD as: [a] general term for a deposition process in which the material to be deposited is released from the source of the material largely by one or more physical mechanisms. He characterized CVD as: [a] deposition process in which a vapor formed with one or more chemical species that contain the material to be deposited, or components of the material to be (. . . continued) deposition such that the titanium nitride layer extends at least into the opening, the titanium nitride layer being less than 25 nm thick; heating the titanium nitride layer while exposing the titanium nitride layer to nitrogen and/or a nitrogen compound; and then forming a tungsten layer over and in physical contact with the titanium nitride layer by chemical vapor deposition such that the tungsten layer also extends at least into the opening."

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deposited, undergoes suitable chemical reaction that enables the material being deposited to be released from the starting chemical species and accumulate on the deposition surface. Later, the Examiner rejected all claims over a second reference, U.S. Pat. No. 6,110,789 ("Rhodes"), which disclosed all of the claimed process steps, including forming TiN layers by PVD to the required thinness (Ex. I at 3-5). Fortin then amended his claims to include a "rounding" limitation in each of the independent claims prior to forming the TiN layer and argued for patentability over Rhodes based on "rounding" (Ex. J at 8-11): In short, the top-edge rounding act recited in Claim 1 or 38 is not merely an act performed as a matter of design choice. Instead, the rounding act is a significant factor in achieving the volcano-reduction objective of the invention . . . The absence of such a disclosure or suggestion combined with the significant nature of the rounding act in Claim 1 or 38 is further reason why Claims 1 and 38 are patentable. In his disclosure, however, Fortin does not teach how such "rounding" achieves the stated objective of improving barrier layer durability, how "rounding" should be measured, or what degree of "rounding" is necessary to achieve that objective. Indeed, he states that, "Why the thinner TiN layers provide better protection is not clear. Without limiting the invention to any particular theory, it is suggested that perhaps one reason is a lower stress in the thinner annealed layers . . ." (Ex. A at 1:67-2:5). Further, Fortin also describes the anneal step as contributing to the objective of improved durability of the barrier layer (Ex. A at 4:13-17), such that it is not clear how effective or essential "rounding" is to achieving that objective when used in combination with effective anneal parameters, or how much rounding is necessary under these circumstances. That is, nothing in the disclosure teaches or suggests what combination of the rounding and anneal steps would achieve the stated objective of improving the durability of the barrier layer; nor does the disclosure include how such a determination should be made.

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II.

FORTIN CLAIM CONSTRUCTIONS Claim construction is a question of law. Markman v. Westview Instruments, Inc., 52 F.3d

967, 977-78 (Fed. Cir. 1995), aff'd 517 U.S. 370, 388-90 (1996). A claim term should be construed to mean "what one of ordinary skill in the art at the time of the invention would have understood the term to mean." Id. at 986. Unless the inventor clearly supplies a different meaning, courts should interpret the language of the claim by applying the ordinary and customary meaning of the words in the claims. Prism Techs. LLC v. Verisign, Inc., 2007 WL 988564, at *1 (D. Del. Apr. 2, 2007) (citing Envirotech Corp. v. Al George, Inc., 730 F. 2d 753, 759 (Fed. Cir. 1984)). Claim construction must be based on the context of the entire patent, including the specification and claims. Phillips v. AWH Corp, 415 F.3d 1303, 1313-17 (Fed. Cir. 2005). The prosecution history may also provide guidance as to the meaning of the claim terms and inform how the inventor understood the invention, including whether the inventor limited the invention in the course of prosecution to make the claim scope more narrow. Id. at 1317; Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1384 (Fed. Cir. 2005). A court may consider the extrinsic evidence, including expert and inventor testimony, dictionaries, and learned treatises, for assistance in understanding the technology, the meaning of terms to one skilled in the art, and how the invention works. Phillips, 415 F.3d at 318-19. A. "physical vapor deposition" and "chemical vapor deposition"7

The terms PVD and CVD have well-established meanings as noted above, and Fortin's usage in the claims and specification is entirely consistent with their ordinary meaning. Moreover, Fortin made clear during prosecution that he was using those well established

7

The claim chart at TAB 1 identifies the claims in which the disputed Fortin terms appear.

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meanings and that the processes are mutually exclusive, i.e., a process can be one or the other, not both. The ordinary meanings of PVD and CVD include at least three essential notions relating to their end result and way of achieving the end result. First, as the terms on their face require and as is clear from the purpose of PVD and CVD, both result in the "deposition" of material on a surface, i.e., that material accumulate (Fortin's term) or build up on a surface. The

accumulation or building up of material is a fundamental feature of deposition processes, as is clear from all the cited references above and the patent itself, and it distinguishes them from, for example, removal processes such as cleaning or etching, which remove material. Second, as noted above, CVD and PVD involve the deposition of material out of a "vapor" or gas phase to form a solid film on the deposition surface. Third, the processes involve certain mechanisms of action. In the case of PVD, the material is released by physical action from a source and then deposited on the surface. In the case of CVD, chemical reactions between the starting reactant gases on the substrate surface produce the material deposited on the surface. (Ex. E, Wolf at 149 (CVD), 434 (PVD)). As explained below, Freescale's proposed definitions of PVD and CVD address and make clear these essential aspects and the distinguishing features of the processes, while ProMOS's do not. Moreover, Freescale's proposed definitions include the essential and

incontestable notion that CVD and PVD are distinct (as Fortin represented to the Patent Office in order to obtain issuance of the patent), while ProMOS's proposed constructions do not.
"physical vapor deposition" Freescale's construction of PVD A process of building up material on a surface in which the material to be deposited is released from a source of the material into a vapor phase by one or more physical mechanisms. Chemical vapor deposition is not physical vapor deposition or a type of physical vapor deposition.

ProMOS's construction of PVD A process in which films are deposited atomically by means of fluxes of individual neutral or ionic species.

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"chemical vapor deposition" Freescale's construction of CVD A process of building up material on a surface in which a vapor formed with one or more chemical species that contain the material to be deposited, or components of the material to be deposited, undergoes suitable chemical reaction that enables the material being deposited to be released from the starting chemical species and accumulate on the deposition surface. Chemical vapor deposition is not physical vapor deposition or a type of physical vapor deposition.

ProMOS's construction of CVD A process in which films are precipitated from the gas phase by a chemical reaction

First, Freescale's definitions include explicitly that CVD and PVD are processes of "building up material on a surface." ProMOS's definition of PVD recites the word "deposition," but does not define it. ProMOS's definition of CVD is even less helpful because not only does it fail to provide a meaning for deposition, it does not even include the term "deposition," as does its PVD definition. "Deposition" is a term that a jury should not have to wonder about when its definition is easily understood. Its ordinary meaning conveys the notion of building up or accumulating on a surface, a notion ProMOS's definition would ignore. Fortin himself in the prosecution history spoke of "accumulation" of the material on the surface (Ex. H at 9). Freescale's definition of "deposition" within its constructions for PVD and CVD is also consistent with other words in the claims (see, e.g., Claim 1: "forming a titanium nitride layer . . .by physical vapor deposition"). That is, the claimed deposition processes result in the formation of a layer such that the layer builds up to a desired thickness during its formation. Phillips, 415 F.3d at 1314 ("[T]he context in which a term is used in the asserted claim can be highly instructive"); see also ACTV, Inc. v. Walt Disney Co., 346 F.3d 1082, 1088 (Fed. Cir. 2003) ("[T]he context of the surrounding words of the claim also must be considered in determining the ordinary and customary meaning of those terms"). Nothing in the claims suggests that deposition should include a step in which a layer is not formed, but is etched (e.g. with a plasma treatment), for example, a notion which ProMOS transparently seeks to include. Second, both processes, as their names suggest, involve deposition of material from a

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"vapor" (i.e., the gas phase of a compound). In PVD, the material to be deposited is released from a starting material into a vapor by a physical mechanism (such as sputtering or evaporation), and then deposited (often by a physical mechanism, such as condensation). In CVD, there is a starting chemical species in a vapor form, and the material to be deposited is released from that species by chemical reaction on the deposition surface (pp. 3-4, supra). Freescale's definitions make clear that there is a vapor in both CVD and PVD, and its proper place in the process. ProMOS's definition of PVD instead uses an obtuse term, "flux," partially addressed to the characteristics of the material during the process (the material flows), but which the jury will not understand and which does not even necessarily have to be a vapor. (All "flux" means is that the material flows, which is true for liquids and gases. See, e.g. Webster's New College Dictionary.) That ProMOS's definition of CVD does at least reference "gas phase" only emphasizes that its definition of PVD is flawed in failing to include the requirement of a "vapor." Third, Freescale's definitions distinguish between the mechanisms of action for releasing material from a starting material in PVD and CVD. In fact, Freescale's definitions closely parallel Fortin's descriptions of the mechanisms of action filed during prosecution, as noted above (pp. 7-8, supra). ProMOS's definition, particularly of PVD, obfuscates the mechanism of action by use of new, obscure terminology nowhere used by Fortin, "deposited atomically by means of fluxes of individual neutral or ionic species." ProMOS's definition of CVD as

requiring a chemical reaction is more understandable, and closer in meaning to the usual terminology (and Freescale's proposed construction mirroring Fortin's language), but it is not a complete definition for other reasons as noted above. ProMOS's definition does not improve upon the description Fortin himself gave of the requirement of a chemical reaction.

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Finally, Fortin's successful efforts to overcome the prior art cited by the Examiner make clear that Freescale's inclusion of what PVD is not (i.e. CVD) is entirely proper. That is, the prosecution history makes clear that the release of material in PVD is by physical, not chemical, action and that CVD is not PVD (Ex. H at 9):
"PVD is a general term for a deposition process "CVD is a deposition process in which . . .the in which the material to be deposited is material to be deposited undergoes suitable chemical reaction to be released from the starting released from the source of the material largely by one or more physical mechanisms" chemical species and accumulate on the deposition surface." "In any event, CVD is not PVD or a type of PVD."

(original emphasis). Accordingly, the definitions here properly should include the distinction urged by the inventor that "CVD is not PVD." See Applied Science & Tech., Inc. v. Advanced Energy Indus., Inc., 204 F. Supp. 2d 712, 715 (D. Del. 2002) (construing disputed limitation in a manner defining what the invention does not encompass based on specification and prosecution history) (citing SciMed Life Sys., Inc. v. Advanced Cardiovascular Sys., Inc., 242 F.3d 1337, 1345 (Fed. Cir. 2001)); see also Phillips, 415 F.3d at 1317 ("Like the specification, the prosecution history provides evidence of how the PTO and the inventor understood the patent."). Only Freescale's definitions reflect the well established meanings of PVD and CVD in the art, and are consistent with their use by Fortin in the patent and his characterizations during prosecution. ProMOS's definitions, on the other hand, would vitiate the claims by improperly omitting various requirements of PVD and CVD. See Oak Tech., Inc. v. Int'l Trade Comm'n, 248 F.3d 1316, 1328-29 (Fed. Cir. 2001) (courts cannot read out a limitation imposed by the claim) (citing Texas Instruments Inc. v. United States Int'l Trade Comm'n, 988 F.2d 1165, 1171 (Fed. Cir. 1993) ("To construe the claims in the manner suggested [by the patentee] would read an express limitation out of the claims. This we will not do because `courts can neither broaden nor narrow claims to give the patentee something different than what he has set forth.").

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B.

"sputtering"
ProMOS's Proposed Construction A process in which atoms from near the surface of a material are physically dislodged by an incoming ion.

Freescale's Proposed Construction A type of physical vapor deposition in which a solid target is bombarded with high energy ions physically to dislodge the surface atoms on the target into a vapor phase for accumulation on the deposition surface without undergoing a chemical reaction.

Unquestionably, "sputtering" is well understood in the art as a particular type of PVD. The Wolf reference, for example, says that "sputtering . . . is the primary PVD method utilized in [certain chip fabrication] applications" (Ex. F at 434). The particular aspect of sputtering as a PVD method is how it generates the vapor without a chemical reaction. Freescale's definition makes clear that sputtering is a type of PVD and then includes the way that sputtering forms the vapor of the material to be deposited (by bombarding the target). ProMOS's definition,

however, while addressing the beginning part of the process with the dislodgement of atoms from a surface, says nothing about the rest of the process. It omits that sputtering is a PVD process, including that the atoms are dislodged into a vapor phase and that it is a deposition process accumulating material on the deposition surface. There can be no question that Fortin uses "sputtering" in its traditional way as a PVD process. In dependent claims 2, 32, 48, and 54, sputtering is claimed by reference to independent claims 1, 31, 47, and 52 as the particular physical vapor deposition process by which TiN layers are formed. See, e.g., Ex. A at 5:12-13 ("the method of claim 1 wherein the titanium nitride layer is formed by sputtering"). In independent claim 25, sputtering is claimed for forming the TiN layer. Phillips, 415 F.3d at 1314 ("Because claim terms are normally used consistently throughout the patent, the usage of a term in one claim can often illuminate the meaning of the same term in other claims.") (internal citations omitted). The specification consistently describes the invention as directed to PVD of TiN (see pp. 6-8, supra) and makes clear that sputtering is a type of PVD: "The invention is not limited to

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any particular sputtering process, and further is applicable to TiN deposited by physical vapor deposition techniques other than sputtering" (Ex. A at 4:49-52). If there were any doubt, Fortin removed it when, during prosecution, he stated that "sputter deposition is a type of PVD" (Ex. H at 10; see also id. at 11). Freescale's definition of sputtering within the framework of physical vapor deposition is thus compelled by the patentee's own use of the term consistent with its use in the art. ProMOS's definition is incomplete and has no foundation in the art or the intrinsic record. C. "rounding"
ProMOS's Proposed Construction Reducing the sharpness of the top edge of the opening.

Freescale's Proposed Construction This term is indefinite.

Independent claims 1, 25, 31, and 47 include the limitation "rounding the top edge of the opening" while dependent claims 18 and 42 include variations thereof. Because the claims with the "rounding" limitation do not reasonably apprise one of ordinary skill in the art of their scope, the claims are indefinite. Section 112, ¶ 2 requires patentees to "particularly point[] out and distinctly claim[] the subject matter which the applicant regards as his invention." Under § 112, ¶ 2, a claim must allow one skilled in the art to determine "the bounds of the claim when read in light of the specification." Allen Eng'g Corp. v. Bartell Indus., Inc., 299 F.3d 1336, 1348 (Fed. Cir. 2002). That is, the focus of a § 112, ¶ 2 inquiry is "whether the claims, as interpreted in view of the written description, adequately perform their function of notifying the public of the [scope of the] patentee's right to exclude." Honeywell Int'l, Inc. v. ITC, 341 F.3d 1332, 1338 (Fed. Cir. 2003). Analysis of claim indefiniteness is a question of law that is properly considered at the time of claim construction. See Atmel Corp. v. Info. Storage Devices, 198 F.3d 1374, 1379 (Fed. Cir. 1999) (indefiniteness analysis is "inextricably intertwined with claim construction").

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The "rounding" limitation renders the claims indefinite because it does not permit one skilled in the art to determine the bounds of the claims in light of the specification and, therefore, to assess or avoid infringement. The specification describes the desirability of rounding the top edges of the claimed opening prior to TiN deposition to allegedly reduce stress in the TiN barrier layer and improve the durability of the barrier layer (Ex. A at 2:59-3:2). It further discloses, however, that preferred annealing parameters contribute to improved durability in TiN barrier layers as well (Ex. A at 4:13-17). Nothing in the patent teaches, suggests, or claims the degree of rounding required to achieve the stated objective, or how, or against what baseline, such a measurement would be made so that a competitor or other potential infringer could determine whether the limitation is satisfied. Amgen Inc. v. Hoechst Marion Roussel, 314 F.3d 1313, 1342 (Fed. Cir. 2003) (claims must be "sufficiently precise to permit a potential competitor to determine whether or not he is infringing.") (internal citations omitted). Nor does ProMOS's construction ("reducing the

sharpness of the top edge of the opening") cure the uncertainty. Rather, by introducing a subjective quality (sharpness) to a competitor's determination of whether the limitation is met, ProMOS confirms its indefinite nature. Furthermore, trying to determine the amount of rounding necessary to achieve the stated objective would be particularly futile in light of Fortin's disclosure of the contribution of proper annealing parameters to achieving the stated objective. Id. (finding indefinite a claim requiring comparison to moving target since the patent failed to direct those of ordinary skill in the art to a standard by which the appropriate comparison could be made). For all of these reasons, the term "rounding" is fatally indefinite.

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THE CHAN PATENTS I. CHAN TECHNOLOGY The Chan patents relate to cache technology. U.S. Pat. No. 5,488,709 ("the `709 patent") is directed to a cache chip and is titled "Cache Including Decoupling Register Circuits." U.S. Pat. No. 5,732,241 ("the `241 patent") is directed to a system that includes a cache chip and a cache controller and is titled "Random Access Cache Memory Controller and System." Both the `709 and `241 patents claim priority to the same abandoned patent application, and only the Abstract and 15 lines in the Summary of the Invention differ between the two patents. The remaining differences are cosmetic.8 Because the specifications are essentially the same, for convenience the `709 specification will be cited. The claims for both patents were rejected by the Patent Office several times. Consequently, Chan had to significantly narrow his claims before convincing the Patent Office to issue his patents. As also described below, the Chan patents were expressly directed to two specific semiconductor chips; indeed a large portion of the specification for the Chan patents was copied verbatim from product literature for those two products. A. Cache Memory

A cache is a memory device into which frequently used data is duplicated so that the data can be more quickly accessed by a computer's central processing unit (CPU) (Ex. 3, i486 Microprocessor Hardware Manual, at 6-1).9 The cache stores some of the same data stored in the computer's main memory (also known as "system" memory). (Id.) The cache is located

8

9

The `709 specification is 78 columns while the `241 is only 64 columns because "Table I" and "Table II" were printed in single-column format in the `709 patent (see Ex. 6 at 10:5632:36) but in dual-column format in the `241 patent (see Ex. 7 at 10:48-22:54). A CPU is also known as "processor," "microprocessor," or "host." In fact, those terms are used interchangeably in the Chan specification. See infra Part IV.F.

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closer to the CPU and is a type of memory that has faster access than system memory. (Id.) Using a cache thus allows the computer to operate faster because frequently accessed information can be retrieved more quickly from the cache than from the slower main/system memory. (Id.) When the CPU wishes to read or write data to or from a particular main memory address, a check is made to determine whether the cache has a copy of the requested memory location. (Id. at 6-2.) If so, then what is known as a "cache hit" occurs. (Id.) If the cache does not have a copy of that memory location, then what is known as a "cache miss" occurs. (Id.) In the case of a "cache miss," the CPU has to access system memory to either read or write the data. (Id.) Accessing system memory slows down the CPU because system memory operates at a much lower frequency (i.e., fewer cycles per second) than the CPU. (Id.) The CPU has to stop its operation to wait for the slower system memory to read out or write data. (See id.) In the case of a "cache read hit," the CPU can read the data from the cache much quicker than it can with system memory. (Id.) For a "cache write hit," data that has been modified by the CPU is saved to the cache. (Id. at 6-11.) At some point, this modified data must also be saved (i.e., written back) to system memory. (Id.) The timing of the modified data being written back to system memory depends on whether the applicable cache is "write-back" or "write-through." (Id.) In a "write-through cache," every time the CPU writes to the cache, the data is also written to the underlying system memory location. (Id.) In a "write-back cache," the cache instead tracks which of its locations have been written over with modified data, and marks these locations "dirty" (i.e., the data is modified but was not yet saved to system memory). (Id. at 6-12.) Because a cache has limited size, when new data is to be saved to the cache, other data must often be "evicted" or

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"evacuated." (See id.) If the data to be evicted is marked "dirty," that gets written-back to system memory. (Id.) The table below provides a glossary of the basic cache-related terminology:
cache CPU system memory cache write hit cache read hit cache write miss cache read miss write-back cache a memory element (usually SRAM) that stores data that is frequently used by the central processing unit also called the central processing unit, processor, microprocessor, or host, it is the "brains" of the computer also called main memory, it is the memory (usually DRAM) that stores the data needed by the CPU CPU wants to write to a particular address in system memory and that address is found (i.e., "hit") in the cache, so that the CPU can write data to the cache CPU wants to obtain data from a particular address in system memory and that address is found in the cache, so the CPU is able to obtain that data quickly from the cache CPU wants to write to a particular address in system memory, but that address is not found (i.e., "miss") in the cache, so the CPU has to access system memory to store the data CPU wants to obtain data from a particular address in system memory, but that address is not found (i.e., "miss") in the cache, so the CPU has to access system memory to obtain the data when a write is made to system memory at a location that is currently cached, the new data is written only to the cache, not actually written to the system memory. Later, if another memory location needs to use the cache line where this data is stored, it is saved ("written back") to the system memory and then the line can be used by the new address. every time the processor writes to a cached memory location, both the cache and the underlying memory location are updated. indicator (often a single bit of memory) that indicates whether the cache location contains data that has been modified and thus must be written-back to system memory removing data from the cache to make room for new data

write-through cache dirty or "dirty bit" evacuation or eviction

B.

Internal vs. External Cache

A cache may be internal or external to the CPU. (See id. at 1-2.) A cache that is "internal" is part of the same integrated circuit (or "IC") as the CPU, which means they both are on the same semiconductor chip. (See id.) An internal cache (in grey) is shown in Figure 2-1 below, which is a page from the reference manual for a particular CPU, the Intel 80486. (Id. at 2-2.) Figure 2-1 illustrates the internal components of the CPU (within gold area), which is the same "i486 Processor" depicted in Figure 1-4. (Id. at 1-9.) The Chan patents properly

acknowledge that the 80486 microprocessor includes an internal cache, and that this internal cache is prior art to the Chan patents. (`709 at 2:66-3:1; 3:17-32).

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A cache that is "external" to the CPU is located on a different semiconductor chip than the CPU. (See id. at 1-8.) Figure 1-4 from the 486 manual shows how an external cache chip (labeled "SRAM" and in green) and a cache controller chip (in blue) could be connected to the 486 CPU chip (in gold). (Id. at 1-12.) As shown in Figure 1-4, the various chips are connected to each other via a "bus," which is a group of conductors that, unlike a point-to-point connection, can permit communication among several devices. (See id. at 3-1.) The processor bus (in purple) depicted in Figure 1-4 is also shown in Figure 2-1 and connects the CPU chip to other devices on other chips (not shown). (Id.) The Chan patents also illustrate the connection of an external cache chip (labeled 72A, 72B, 72C and 72D in Figure 7 and 72 in Figure 32) and an external controller chip (labeled 70 in Figures 7 and 32) to a 486 CPU chip (labeled 60). Patent Figures 7 and 32 provide an overall

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system-level view of the connection. Figure 13 illustrates in more detail the connection between specific pins on the cache memory chip and specific pins on the 486 CPU chip. Semiconductor chips come in a variety of packages, a few of which are illustrated below.10 The chips have terminal pins or "pins" that are used as ports for inputting or outputting signals such as data. The pins, shown at the bottom of each figure below, are connected to a bus of the type shown in Figure 1-4 above.

As described below, the prosecution history, specification, and claims make clear that the `709 and `241 claims are directed to a cache chip that is external to the CPU.

10

The three most common types of chip packages are DIPs (Dual In-line Packages), which have anywhere from 8 to 40 pins evenly divided in two rows, PGAs (Pin-Grid Arrays), in which the pins are arranged in concentric squares, and SIPS (Single In-line Packages), which have just one row of pins in a straight line like a comb.

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II.

THE CHAN PATENTS A. Overview of the `709 Patent
1. A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register for buffering first data received from said host port and selectively providing the first data to one of said random access memory, said system port, and said random access memory and said system port, said memory write register being coupled between said host port and said random access memory and between said host port and said system port; and a write back register for holding second data received from said random access memory and selectively providing the second data to said system port, said write back register being coupled between said random access memory and said system port; wherein the buffering and selective providing of the first data to said random access memory and the holding and selective providing of the second data to said system port allows memory accesses at said host port to be decoupled from memory accesses at said system port.

Claim 1 of the `709 patent is directed to a cache memory apparatus. As described in the Chan specification, and as demonstrated by the prosecution history, the claimed "cache memory apparatus" is external to the CPU chip. That is, the cache memory apparatus is itself a chip. As shown in Figure 12A (with structure in claim 1 emphasized), the cache chip is connected to the CPU via a "CPU port," which is called a host port in claim 1, and to the system memory via a "system port." Thus, the host and system ports supply the pins connecting the cache chip to the processor bus and system bus described above in Figure 1-4 in connection with the 486 processor.11 The `709 cache chip has a memory write register 120 that receives data from the CPU host port and then can selectively provide the data to one of (i) the random access memory 100,12

11 12

See supra Part I.B An example of this action would be a "cache write hit" in a "write-back cache," as described in Part I.A.

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(ii) the system port,13 and (iii) both the random access memory and system port.14 (`709 at 4:920; 32:36-48.) As discussed above, because the system memory is slower than the CPU, the memory write register can temporarily hold or buffer the data, which allows the CPU to perform other operations while the memory write register completes the write to system memory. (See id. at 32:36-48 (noting "zero wait states" needed).) The cache chip also has a write back register 118 for holding data that is received from the random access memory 100. (Id. at 10:27-30.) The write back register 118 selectively provides this data to the system port. (Id. at 33:12-16.) That is, depending on certain conditions present at the time, the write back register either (i) provides or (ii) does not provide the data to the system port.15 (Id.)

13

14

15

An example of this action would be where the CPU wants to write to a "non-cacheable address." That is, for some reason the computer is configured so that certain address locations in main memory are not allowed to be replicated in the cache. An example of this action would be a cache write hit in a write-through cache, where every cache write causes a write to system memory, as described in Part I.A. As described in Part I.A, if the data evicted from the cache RAM array is "dirty," the data must be written back to system memory. If the data evicted is not dirty, the data is not written back (i.e., not "provided") to system memory.

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B.

Overview of the `241 Patent
1. A computer system comprising: a host processor having a host address bus and a host data bus; a system memory having storage locations addressable by said host processor, a system address bus and a system data bus; a dual port cache memory having a system port connected to said system data bus and a host port connected to said host data bus, said dual port cache memory comprising cache storage locations dynamically associable with said storage locations of said system memory and a plurality of registers coupling said cache storage locations to said host port and said system port, wherein a data path between said host data bus and said system data bus is operably decoupled by buffering and selective provision of data to and from said cache storage locations by said plurality of registers so as to allow concurrent transfer of data to and from said dual port cache memory; and a cache controller connected to said dual port cache memory, said cache controller having a first port connected to said host address bus and a second port connected to said system address bus such that said dual port cache memory and said cache controller are connected in parallel between said host processor and said system memory.

The `241 patent is directed to a "computer system" comprising (1) a host processor, (2) a system memory, (3) a cache controller, and (4) a dual port cache memory.16 The specification and the prosecution history of both the `709 and `241 patents clearly state that the claimed "cache controller" and "dual port cache memory" are both stand-alone chips that are external to the host processor (i.e., CPU) chip.17 Figure 32 is a block diagram of the `241 system and shows how the cache controller chip ("MS441 Cache Controller") and dual port cache memory chip ("MS443 Dual Port Burst Memory") connect to the host processor ("486 or 386 CPU") and system memory ("DRAM").

16

17

Independent claims 1, 15, and 16 are directed to a computer system, while independent claim 10 is directed to a "method for operating a memory cache apparatus." See infra Part III.

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In claim 1 of the `241 patent, the dual port cache memory chip has the same "host port" and "system port" as in the `709 patent; these ports connect to the data buses that connect to the CPU (in gold) and the system memory (in red). In place of the various registers shown in Figure 12A, claim 1 recites "a plurality of registers" that are within the cache memory chip. In the `241 patent, both CPU and system memory connect to ports on the cache controller chip via an address bus. III. THE CHAN INTRINSIC RECORD Claim construction should not be done in a vacuum. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005). Rather, claim construction must be based on the context of the intrinsic evidence, including the specification, claims, drawings, and the prosecution history. Id. at 1313-17. The specification is "the single best guide" to the meaning of the claims, and it alone is "usually dispositive." Id. at 1315. Where the preferred embodiment in the specification is described as the invention itself, the claims are not entitled to a broader scope than the embodiment. Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1384 (Fed. Cir. 2005). A. The Prosecution History Demonstrates That The Chan Patents Are Directed To An External Cache 1. The Specification Of The `709 And `241 Patents Was Copied From MOSEL's Product Literature Describing An External Cache

The inventor of the two Chan patents, Albert K. Chan, worked at Intel Corporation as a design engineer. Intel Corporation sold two widely-used microprocessors, the 80386 ("386") and 80486 ("486"), the latter of which was discussed above. After leaving Intel and joining MOS Electronics Corp. ("MOSEL"), which was the original assignee of the Chan patents, Mr. Chan allegedly developed a cache memory chip called the MS82C443 and a cache controller chip called the MS82C441. As reflected in their data sheets, the MOSEL chips were specifically designed to work with Intel's 386 and 486 chips and as such, both are external chips.

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(See Ex. 1.)18 The specification for the `709 and `241 patents was largely copied from MOSEL product literature. In fact, when the original patent application from which both patents claim priority was filed, instead of using his own words to describe his invention, Chan simply attached a 26page MOSEL cache chip specification and a 50-page MOSEL Burst RAM architecture specification. (See Ex. 4; 5.) After the Patent Office rejected all the claims, Chan filed the `709 application and added to the specification by copying wholesale parts of additional MOSEL documents. For example, Figures 5, 7, 9, 10, 12b, and 13 through 31 and Table II (see `709 at col. 29-32) are taken verbatim from the MOSEL MS82C443 Burst-RAM datasheet. (See Ex. 2.) As demonstrated below, both the prosecution history and patent specification reaffirm that the `709 and `241 patents were intended to patent the specific MOSEL chips that Mr. Chan developed to work with the two Intel CPU chips. Because those chips are external, the claims in the `709 and `241 patents are limited to an external chip. 2. The `709 Claims Were Amended Four Times And Incorporated Limitations From The MOSEL Cache Chip Each Time

During prosecution of the `709 patent, Chan attempted to claim something much broader than the particular cache chip he developed, but the Examiner repeatedly rejected the claims. (See Ex. 8-11.) After the claims had been rejected twice and Chan had narrowed his claims twice (see Ex. 12-13), in the third office action, the Examiner stated: Note also that the mere labeling of a register (such as an "update" or "miss (hit)" register) without a recitation of its function or operation does not render the claimed invention patentably distinct.

18

The MOSEL data sheets note certain "on chip" features and provide a "pinout" that lists the signals for the various pins for connection to other chips.

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(Ex. 10 at 8.) After Chan narrowed the claims for a third time (see Ex. 14), the Examiner again rejected all the claims, adding: Applicant has not adequately addressed the explanation provided by the Examiner of how the claimed "system port," "host port," "input registers," and "output registers" are met by the references. Again note that the mere labeling of a register (such as an "update" register) without a clear recitation of its function and operation does not render the claimed invention patentably distinct. The functional language "the writing...and...providing of data...'allowing' the host port to be decoupled" is not sufficient to patentably define the claimed invention over the prior art. (Ex. 11 at 6.) In response to this rejection, Chan amended the claims to finally add enough structural and functional limitations describing how his invention worked (see Ex. 15) and the Examiner allowed the claims. As support for these additional limitations, Chan cited to the text that is found in the `709 specification at 32:37-34:2 and 39:26-40:7. (Id. at 13-14.) 3. The `241 Claims Were Amended Five Times And Incorporated Limitations From The MOSEL Chips Each

Including the original priority application and the continuation application, the `241 claims were rejected five times (see Ex. 8; 16-19), and after each rejection, Chan narrowed the claims. (See Ex. 20-24.) Although the `709 and `241 patents were examined by different Examiners, the `241 Examiner also made a statement about the broad claims that Chan was attempting to patent: A cache memory is a fast memory element and without specific caching details appearing in the claims, any memory element, especially one designated by the reference as a cache is considered equivalent to a cache memory unless specific details of the claimed cache are present in the claims. ... As to the input registers, the holding registers and output registers are taught to the extent claimed. (Ex. 19 at 2 (emphasis added).) The `241 claims, like the `709 claims, also were not allowed until Chan narrowed his claims to (as the applicant admitted) "obtain a more appropriate scope of coverage." (Ex. 24, Paper 25 at 7.) As support for adding the "data path," "decoupled," and "plurality of registers"

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limitations, for example, Chan cited to the text that is found in the `709 specification at 3:64 to 4:2; 41:25-43; and 43:20-32. (See Ex. 21 at 8-9.) 4. During Prosecution, The `709 And `241 Claims Were Limited To An External Cache Chip

In narrowing the claims to patentably define over the prior art and obtain his patents, Chan repeatedly cited portions of the specification copied from product documentation describing the MOSEL external cache chip. As support for adding the "write back register" limit