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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE PROMOS TECHNOLOGIES, INC., Plaintiff, v. FREESCALE SEMICONDUCTOR, INC., Defendant. ) ) ) ) ) ) ) ) ) )
C.A. No. 06-788 (JJF)
APPENDIX TO FREESCALE'S OPENING CLAIM CONSTRUCTION BRIEF VOLUME IV; EXHIBITS RELATING TO THE CHAN PATENTS CHAN FILE HISTORIES AND DICTIONARIES
MORRIS, NICHOLS, ARSHT & TUNNELL LLP Mary B. Graham (#2256) James W. Parrett, Jr. (#4292) 1201 N. Market Street P.O. Box 1347 Wilmington, DE 19899-1347 302.658.9200 OF COUNSEL: David L. Witcoff Kevin P. Ferguson John M. Michalik JONES DAY 77 West Wacker Chicago, IL 60601-1692 312.782.3939 F. Drexel Feeling JONES DAY North Point 901 Lakeside Avenue Cleveland, OH 44114-1190 216.586.3939 Dated: November 6, 2007 Attorneys for Freescale Semiconductor, Inc.
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TABLE OF EXHIBITS EXHIBIT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION `071 abandoned application paper 5 Paper 6 from `709 File History Paper 8 from `709 File History Paper 13 from `709 File History Paper 8 from `709 File History Paper 7 from `709 File History Paper 10 from `709 File History Paper 15 from `709 File History Paper 5 from `241 File History Paper 9 from `241 File History Paper 17 from `241 File History Paper 24 from `241 File History Paper 2 from `241 File History Paper 8 from `241 File History Paper 12 from `241 File History Paper 22 from `241 File History Paper 25 from `241 File History Paper 20 from `241 File History IBM Dictionary of Computing (10th ed. 1993) excerpts Microsoft Press Computer Dictionary (3d. ed. 1997) excerpts The New IEEE Standard Dictionary of Electrical and Electronics Terms (5th ed. 1993) excerpts
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EXHIBIT 16
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UNITED STATES DEPARTMENT OF COMMERCE
k1~TiPatent and Trademark Office
(D
SEILNMEnRIOAEFRST
Address:
COMMISSIONER OF PATENTS AND TRADEMARKS
Washington, D.C. 20231
NAMED INVEWIDA CHAN
___
TORNEY DCE A M-1010--2P-US
O
07/678,914
04/01/91
EELFMOE,
EXAMINER
B. NOEL KIVLIN SKJERVEN, MORRILL, MACPHERSON, FRANKLIN & FRIEL 25 METRO DRIVE, SUITE 700 SAN JOSE, CA 95110
This It a communicabon !non the examiner incharge aF vou~r application.
CY)MMISSIONESR OF PATENTS AND TRAD IlIRKS
ATUNIT 23125
DATE MAILED:
LAERNMER
0 1/14/93
W This application has been examined
EI] Responsive to communication filed on___________ E]1: action is made final. This
A shortened statutory period for response to this action is set to expire ______month(s), _____ days from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned. 35 U.S.C. 133 Part I THE FOLLOWING ATTACHMENT(S) ARE PART OF THIS ACTION: 1.9 Notice of References Cited by Examiner, PTO-892. 3. Notice of Art Cited by Applicant, PTO-1449.
S.
2. a 4.
6.
Information on How to Effect Drawing Changes, PTO-1 474,
[]Ir Notice of Informal Patent Application, Form E
__________________
Notice re Patent Drawing, PTO-948.
PTO- 152
Pant H SUMMARY OF ACTION 1.VLJCIaims k14ti are pending in the appiKration. are withdrawn from consideration. have been cancelled. are allowed.
Of the above, claims 2. 3. Claims
ElClaims
1
4. 1;g-Claims 5. 1:1 claims
/
Iare
rejected, are objected to.
are subject to restriction or election requirement.
6. E] claims________________________________
F] This application has been filed with informal drawings under 37 C.F.R. 8. FM Formal drawings are required in response to this Office action.
7.
1.85 which are acceptable for examination purposes.
9. El The corrected or substitute drawings have been received on ______________.Under are [3 acceptable; 0 not acceptable (see explanation or Notice re Patent Drawing, PTO-948).
10.
37 C.F.R. 1.84 these drawings
F]The proposed
additional or substitute sheet(s) of drawings, filed on examiner; 03 disapproved by the examiner (see explanation).
___________,has
_________
has (have) b,een E3 approved by the
11.
FlThe proposed drawing correction, filed '12. FlAcknowledgement is made of the claim for priority under
E3 been filed In parent application, serial no. ___________
been 0 approved; 0 disapproved (see explanation). U.S.C. 1119. The certified copy has LI been received C3 not been received
filed on
___________
I&.F Since this application apppears to be in condition for allowance except for formal matters, prosecution as to the merits Is closed in
accordance With the practice under Ex parte Quayle, 1935 C.D. 11; 4530O.G. 213.
14.
lOther
EXAMINER'S ACTION
PTOL-326 (Rov.9-89)
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C
Serial Number 07/678,914 Art Unit 2312 1. 2. Claims 1-14 are presented for examination. The title of the invention is not descriptive.
-2--
A new title
is required that is clearly indicative of the invention to which the claims are directed. 3. The current'titie is imprecise.
The letter filed 3-16-92 concerning small entity status has Applicant is referred to MPE?
been entered into the f~ile.
509.03, pages 500-1516,,column 2, paragraph 2 et seq. 4. The Abstract of the Disclosure is objected to because the
abstract can not contain more than one paragraph., Applicant is reminded of the proper language and format of an Abstract of the Disclosure. The abstract shoul d be in narrative form'and genetall~ limited to a singlie par agraph on a separate sheet within K range of 50 to 250 word's. It is important that the abstract not exceed 250 words in length since the space provided for the abstract on the cqmputer. tape used by he printer is limited. The form and legal phraseology often used in patent claims, such as 'means' and "said', should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise ahd should not It should avoid using repeat information given in the title. phrases which can be implied, such as, "The disclosure concerns," 'The disclosure defined by this invention, " "The disclosure describes,' etc. Correction is required. 5. See M4.P.E.P. § 608.01(b)". The disclosure is objected to because of the following
informal ities: (a) It is noted that although the present app1lication doe's contain line numbers in'the specification and claims, the line numbers in the cla:ims do not correspond to the preferred format. It is suggested that every fifth line of every claim be numbered, with eaAh new claim begLinning with line 1. For ease of reference
1 ,by both the examiner anidapplicant all future correspondence
should include the recoimmended line numbering.
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Serial Number 07/678,914-3 Art Unit 2312 Appropriate correction 'is required. 6. Claim 1-14 are rejected under 35 USC 112, second paragraph,
as being indefinite for failing to particularly point, out,and distinctly claim the subject matter which applicant regards as the invention. (a) The -claims are indefinite because: It is unclear: as to where the plurality of cache
addresses are stored and as to how a comparison is achieved in claim 1. (b) It is unclear, as to what is meant by "replaced data" in It is unclear' as to what is actually occuring in the
claims I and 2. (ci) step of "providing said: replaced data to said system port" because making the data available to a port does not appear to be a constructive step. In fact, the step which recites "is provided' appear to be unclear,and indistinct in-that "providiing" or "making available" does not constitute an action because the data is not transferred or used in any way, it is only present. A step in a method, claim which does not perform an action is indefinite in nature. and 12-13. (d) 5; (e) It is unclear in claim 10 as to why data must be loaded from a peripheral,device' when the claim states tlier'e is a hit condition in the dual port cache memory. (f) claim 13. 7. The following is a'quotation of the appropriate paragraphs "the furtther step" lacks clear antecedent basis
-
This rejection applies method-claims 1-3
"the same time" lacks clear antecedent basis
--
claim
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ýSeria1 Number 07/678,9.14 Art Unit 2312
-4-
of 35 U.S.C. S 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless
--
(b) the invention was patented or described in a.printed publication in this or a foreign'country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States. 8. Claims 1-8 and 11-14 are rejected under 35 U.S.C.
§102(b) as being anticipated by Thomas et al.
Thomas teaches the invention (claim 4) including a computer system comp$rising: (a) (b) (c) (d) a processor (e.g., see Figure 1); a systemi memory (e.g., see Figure 1); a dual port cache (e.g., see F~igure 1); and, a cache controll er (e.g.) see Figure 1). as claimed,
As to claim 5, Thomas teaches providing an-~address to th6 move out queue which is different from the address requested by the processor (e.g., see col. 5, lines 40 et seq.). As to claim 6, Thomas teaches data can be -transferred on the host bus asynchronously to data transferred on the system bus (e.g., see col. 5, lines 40 et seq.).
As to claim 7, Thomas teaches controlling the addressiAýg sequence for the system memory on the system bus and controlling the addressing sequence for the processor on the host bus (e.g., see col. 5, lines 40 at seq.)..I As to claim 8, Thomas teaches the system bus does not need to be accessed for a cache hit condition but that this is a local bus access request (e.g., see col. 2, lines 50 et seq.). Asy,to claim 11, Thomas teaches system memory operates at a .different frequency that the processor (e.g., see col. 1, lines 18 et seq.).
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Serial Number 07/678,914 Art Unit 2312
-5-
As to claim 12, Thomas teaches when data is provided from system memory for a processor request, the data is sent directly to the processor (e.g., see col. 4, lines 32-55). Method claims 1-3 and 13-14 do not teach or define over the above rejected apparatus claims and are rejected on the same basis. 9. The following is a quotation of 35 USC S 103 which forms the
basis for all obviousness rejections set forth in this Office action: Ajpatent may' not be obtained though the invention is not identically disclosed or described as set. forth in section 102 of this title; if the differences between the subject matter sought to be patented and the prior art are,such that the subject matter as a whole would have been obvious at the time the invention was made to a pe~rson having ordinary skill in thelart to which said subject matter pertains. Patentability' shall. not be negatived by the manner in which the invention wasi,made. Subject matter developed,by another person-;- which qualifies as prior art only,undert,subsection (ft)or (g) of section 102 of this t itle, shall not preclude patentability under this section where the subject matter and the claimed invention were, at the time the invention was made, owned by the sam-e person or subject to an obligation of assignment to the same person. 10, Claims 9 and 10 are rejected under 35 USC §103 as being Claims 9 and 10 are directed to peripheral -memory devices for storing data which,may or may not be needed during the course of processing. It is common practice in the memory arts to use The use of maintaining part of the low cost storage, such as disk storage, when this type of processing situation occurs. data in peripheral~ stortage and moving in blocks of data as the processor requests data~ only resident on the peripheral storage is well l4 own andl,official notice is taken thereof. It would have beenl obvious to one of ordinary skill in the unpatentable over Thomas et al.
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/Serial Numbbr 07/67B,9 14 Art Unit 2312
-6-
art of memory storage at the time the invention was made to utilize disk storage or other peripheral storage to maintain data which the processor may need for processing because large amounts of periphera.l storage is more-,economnical to use than trying to maintain all data which may be required in the much more expensive system memory or cache memory and the techniques for using such peripheral storage in a cache system are well documented. 11.
This application currently names joint inventors.
In considering patentability of the claims under 35 USC ~103, the examiner presumes that the subject matter of hevarious claims was commonly,owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 'CFR S 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of potential 35 USC § 102(,f) or (g) prior art under 35 USC § 103. The prior art made of record and not relied upon is
12.
considered pertinent to applicant's disclosure. Holland et al. teaches a data processing system having, instructive responsive apparatus for both a basic and an extended instruction set. Ziegler et alk teaches a dual port cache with interleaved read access during alternate half-cycles and simu~ltaneous writing. Mlatick et al.Iteachles a distributed on-chip cache. Mloussouris etial. teaches a CPU chip having a tag comparator and address translaýtion unit on chip and connected to off-chip cache and main memories. 13. Anyinquiry concerning this communication or earlier
communications from the examiner should be directed to Reba. I. Elmore whose telephone number is (703) 308-1619.
I
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K
Serial Number 07/678,914 Art Unit 2312
-7--
Any inquiry of a general nature or relating to the status of this application should'be directed to the Group receptionist whose telephone numnber is (703) 308-0t54.
Reba I. Elmore January 5, 1993
GRWP 2300
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EXHIBIT 17
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,
~~UNITEO,ST-ATE&,,JEPAFtRITME ePatent, and, 'Trademiark-Office
-Address:
.PJT C&(II OF ,
CE_
COMMISSIONERZOFPAT 'ENT-S AND T:RAIEARKSý' Washington, 0.C: 20231
SERIAL NUMBER 0J//678,914
PILING DATE
FIRST NAMED INVENTORATONYDCEI§
04/01/91
CFIAN
EXAMINER
E3M1 /0920
IELMIORE, R
ART UNIT PAPER NUMBER7
B. NOEL KIVLIN\
SKJfERVEN, MORR ILL, MACPHERSON, FRA~NKLI:N & F'RIEL 25 MET-RO DRIVE, SUITE 700 SAN JOSE, CA 951 10
"this is a communicagohi from toe examiner in charge of your aPpptcadon. COMMISSIONER OF PATENTS AND TRADEMARKS i
2312
DATE MAILED: 09/20/93
application~~~~ hsbeexmnd'Reponsive to,communicatilfn-fled tn A shortened statutory period for response to thI acioMAfn Is.stt$ expirea PI3...A...inth(s), <'2;Failure to respond within the period for re'spon)sa w1iicas th aplcto obcm bnoe.
't9s>E
-This action 16 made final.
9t
days from the date'o this letter, SU.S.C. 133 >
Port 1I
1. 3.
THEIFOLL=11OWING ATTACN.MENT(8),AREPATFHIACON Notice of References Cited by Examiner. P0892. Information on How to Effect Drawing Changes, PT0-1474.
1
. Notice of Art Cited byAppicant; FTO-1449.1I
11.El
Parti1i
2. 4. S.
E0 0l
Notice re Patent Drawing; PTO-948.1
E0 Notice of Informal Patent Application, Fornm PTO-152;
SUMMARY OF ACTION
It- Claimns
-
#-are
_______________________________ Ot 0S c.
'/ pending Inthe applicationm
are withdrawn from consideration.
Of the above, claims
2.JClaims3.
/-,
1
have been cancelied.
are allowed.
0l
Claims Claims
4. IX
(
U
are rejected. are objected to.
5.
0l
claims
________________________________ ---
6. E0 Claims 7.
are subject to restriction or eiection requirement.
E0 This application has been filed with Informal drawings under 37 C.F.R.- 1.85 which are acceptable for examination purposes.
8. C3 Formal drawings are required-In response to !this Office action.
o. ElThe corrected
are 10.
Epacpal. El
or substitute drawings have been received on _'.Under 37 C,F.R.-1.84 these drawings* o cetable (see explanation or Notice re Patent. Drawing, PTO-948).'
--
El The proposed additional or substitiuteeheefis).of drawings, tiled on
examiner. disapproved by thelexaminer ; e-ekplanation). (s;
-,has
ý has (have) been
U -aproved by the
11. E0 The propbsed drawing correction, filed on 12.
been
Elapproved. -l-disapproved
-filed on
(seeýexqiianation). not been received
-
03
Acknowledgm n0~s made of the-c$inn for,pripr;tyunder U.&C-.119; The't6rilified-copy has
-0
01 -been*recoiyodý C
been filied In parent applicatior~, serial no'
-
~--
--.
13.;
-accordance
Since this applicaflon.appetrs tob win condit Ion for Ailowance except-for,formal mattens;,pros6cution as tothetmieritt In; closed Inwith the practice undlek Ex parte uayler1935 G-D 11 ,4530o.0.213--ý
14.
0l
Other
V
EXAMINER'S ACTION
PTOL-326 (Rev. 9-89).-
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Serial Number: 678,914 Art Unit: 2312
-2-
1.
Claims 4-li and 15-21 are presented fOr examination.
Claims
1-3 and 12-14 have been cancelled by the amendment filed 6-17-93. 2. The objection to the title is withdrawn due to the
amendment. 3. The objection to the Abstract is withdrawn due to the
amendment. 4. The drawings are objected to because: (a) From the Brief Description of the Drawings, Figures 6
and 7 appear to be prior art and should be so designated. Figures which illustrate prior art should be designated by a legend such as "Prior Art" in order to clarify what is the applicant's invention (see HPEP 608.02(g)). (b) There is not a Figure 8 in the application. Figures
8A, 8B and 80 have not been described in the Brief Description of the Drawings. All references to Figure 8 in the specification
should be corrected; (c) Suitable meaningful legends, (not ambiguous labels or
initials), are required for unlabeled or inadequately labeled drawing elements of Figures 8B and 80 (see 37 CFR 1.84(g)). subarrays of Figure 8B should be so labeled. should be shown in Figure 80 also. Correction is required. Applicant is reminded of the provisions of MPEP 608.02(q) and 608.02.4r) regarding a separate draftsman's letter. 5. The disclosure is objected to because of the following The
Appropriate labels
informalities:
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-3--
(a)
Figure 8 is described in the specification, however
there is not a Figure 8 provided in the drawings. Appropriate correction is required. 6. The rejections under 35 USC 112, second paragraph, are The following rejection under 35
withdrawn due to the amendment.
USC 112, second paragraph, is given due to the amendment. 7. Claim 21 is rejected under 35 USC 112, second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. The claims are indefinite because:
(4) "said system input register" lacks clear antecedent
basis 8.
--
claim 21.
The following is a quotation of the appropriate paragraphs
of 35 USC § 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless
--
(b) the invention was patented or described in a printed publication in this or a foreign country or.in public uAe or on sale in this country, more than one year prior to the date of application for patent in the United States. 9. Claims 4-11 and 15-21 are rejected under 35 U.S.C. § 102(b)
as being clearly anticipated by Holland et al. Holland teaches the invention (claims 4, 15 and 21) as claimed, including a computer system comprising: (a) 35); (b) a system memory (e.g., see Figure 1, element 16); a microprocessor (CPU) (e.g., see Figure 1, element
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(c) (d)
a dual port cache (e.g., see Figure 1, element 17); a host input register connected to the dual port cache
and the host data bus for providing data from the host data bus to the dual port cache (e.g., see Figure 2, element 54); (e) a system output register connected to the dual port
cache and the system data bus for receiving data from the dual port cache memory and providing data to the system memory (e.g., see Figure 2, element 46); (f) a controller connected to the dual port cache memory
and the host address bus is taught as a control processor, the controller compares a host address to the addresses in the dual port cache (e.g., see 0o1. 7, lines 14-38); (g) when a cache match results from the address comparing
of the controller, data from the input register is placed in the dual port cache (e.g., see col. 11, lines 17 et seq.); and, (h) data from the system memory is placed in the cache when
data requested by the CPU is not present in the cache without overwriting host data (e.g.-, see aol. 11, lines 49 et seq.).. As to claim 5, Holland teaches the controller is connected to the cache memory and provides a first address on the host address bus concurrently with providing a second address on the system address bus with the first address being different than the second address (e.g., see aol. 11, lines 17-36). As to claim 6, Holland teaches data transferred from the host to the cache is asynchronous to the data transferred from the cache to the system memory (e.g., see col. 11, lines 17-36).
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AS to claim 7, Holland teaches control sequencing to the extent claimed (e.g., see col. 32, lines 62 et seq.). As to claim 8, Holland teaches disabling the dual port cache (e.g., see Figure 1, element 39). AS to claims 9-10, Holland teaches a peripheral device is coupled to the system memory and that the peripheral device can contain data which may be requested by the CPU and which can be transferred to the dual port cache (e.g., see col. 7, lines 3641). As to claim 11, Holland inherently teaches the CPU and the memory operate at different speeds as dynamic RAM operates at a slower speed than the CPUs of the systems discussed in the Background Of the Invention in columns 1 and 2. As to claim 16, Holland teaches data can be transferred from the CPU to the input register while data is input to the dual port cache (e.g., see col. 10, lines 32-50). As to claim 17, Holland teaches a plurality of data locations can be transferred during one clock cycle (e.g., see col. 15, lines 16 et seq.). As to claim 18, Holland teaches the host port can be coupled to the system port when a read miss occurs (e.g., see Figure 1). As to claim 19, Holland teaches data is placed in the input register in a first clock cycle and data is transferred to the system memory during a second clock cycle (e.g., see col. 11, lines 17 et seq.). As to claim 20, Holland teaches the dual port cache
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comprises a plurality of random access memories (e.g., see col. 9, lines 49-60).
10. Applicant's arguments with respect to claims 4-10 and 15-21
have been considered but are deemed to be moot in view of the new grounds of rejection. 11. Applicant's amendment necessitated the new grounds of Accordingly, THIS ACTION IS MADE FINAL. See M.P.E.P.
rejection.
§ 706.07(a).
Applicant is reminded of the extension of time
policy as set forth in 37 C.F.R. § 1.136(a). A SHORTENED STATUTORY PERIOD FOR RESPONSE TO THIS FINAL ACTION IS SET TO EXPIRE THREE MONTHS FROM THE DATE OF THIS ACTION. IN THE EVENT A FIRST RESPONSE IS FILED WITHIN TWO MONTHS OF THE MAILING DATE OF THIS FINAL ACTION AND THE ADVISORY ACTION IS NOT MAILED UNTIL AFTER THE END OF THE THREE-MONTH SHORTENED, STATUTORY PERIOD, THEN THE SHORTENED STATUTORY PERIOD WILL EXPIRE ON THE DATE THE ADVISORY ACTION IS MAILED, AND ANY EXTENSION FEE PURSUANT TO 37 C.F.R. § 1.136(a) WILL BE CALCULATED FROM THE MAILING DATE OF THE ADVISORtY ACTION. IN NO EVENT WILL THE STATUTORY PERIOD FOR RESPONSE EXPIRE LATER THAN SIX MONTHS FROM THE DATE OF THIS FINAL ACTION. 12. Any inquiry concerning this communication or earlier
communications from the examiner should be directed to Reba. .I. Elmore whose telephone number is (703) 305-3819. Any inquiry of a general nature or relating to the status of this application should be directed to the Group receptionist whose telephone number is (703) 305-9600.
Reba I. Elmore September 18, 1993
MOSEPH L DIXON SUPERMIORY PATENT EXAMINER~ GROUP =30
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EXHIBIT 18
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UNITED STATIES DEPARTMENT OF COMMERCE
Patent and Trademark Office
I ISEIAL NUMBER I
0;S/I 71:', 642
FILING DATE
I
Address: COMMISSIONER OF PATENTS AND TRADEMARKS Washington, D.C. 20231 FISTNAEDINENTOR IATTORNEY DOCKET NO.
12 /20 /93
A
rl.. [S1C [1
EXAMINER
L
BEISM/ 1:218 sTE-.PHEN A. TERRIL.L.' q
II
NUM=BER
E
ART UNIT
IPAPER
]
17
23'18
DATE MAILED:
.1. /18 / 5 2
This application has been examined
ýr$esponsIve to communication,filed on
5
12'_28C'5~
Ashortened statutory period for response to this action Isset to expire ..
Pert[I
... month(s), from the date of this letter. Failure to respond within the period for response will cause the application to become abandonleV35 U.S.C. 133 THE FOLLOWING ATTACHMEN:T(S) ARE! PART OF THIS ACTION: 1 Notice of References Cited by Examiner,' PTO-892.
How to Effect brawing Changes, PTO-1474.,
..... idays
El
This action Ismade final.
2.
6.
El Notice of Draftsman's
E]
____________________
Patent Drawing Review, PTOý9148.
3 Notice of Art Cited by Applicant, PTO-1 449.
54 1rfrainon
4. [1 Notice of Informal Patent Application, PTO-152.
Part 11 SUMMARY OF ACTION 1. xClalms Of the above, claims
Iare
areý pending Inthe applcat Ion. withdrawn from consideratil on.
2.gEVOlalms
3.
L-3
z.LSthave
been ranollied.
are allowed.
ElClaims
SZ_ 51I
4)j'Ciaims S. El Claims
are rejected. are objected to.
e6,E
7.1
Claims__________________________________ are subject to restriction or election requirement. Thsapiainhsbefiewihifradrawings under 37 C.F.R. 1.88 which are acceptable for examination purposes.
E
S. El Formal drawings are required Inresponse tb this Office action.
s. El The corrected or substitute drawings have been received on
10.
11.
37 C.F.R. 1.84 these drawings are [3 acceptable; [3 not acceptable (see explanation or Notice of Draftsman's Patent Drawing Review, PTO-948).
____________.Under
El The proposed
additional or substitute sheet(s) of drawings, filied on ________. examiner; 0l disapproved by the examine( (see explanation). filed
has (have) been E3 approved by the
El The proposed drawing correction,
Ml
i___________ has been f3 approved: L3 disapproved (see explanation).
12. 13. 14.
El Acknowleogement Ismade oft the claim for p~riority under 35
been filed inýparent application, serial no'.
_________
U.S.C. 11 9. The certified copy has [3.been received
;filied on
___________
I3 not been received
El Since this appication apppears to be Incondition for allowance except for formal matters, prosecution as to the merits Isclosed In
accordance with the practice under Ex parts Quayle, 1935 C.D. 11; 453 O.G. 213.
El Other
I
PTOL,326 (Rev. 2193)
EXAMINER'S ACTION
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Serial Number: 08/170,642
-2-
Art Unit: 2318
1. Claims 4-11 and 15-32 are presented for examination. 2. The changes to Figures 8B and 8C are approved by the
examiner, however, applicant is reminded of the provisions of MPEP 608.02(q) and 608.02(r) regarding a separate draftsman's letter. 3. Claim 21 is rejected under 35 USC 112, second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. The claim is indefinite because:
(a) "said data bus" lacks proper antecedent basis, a host data bus and a system data bus have been previously claimed, it is not clear which data bus 'said data bus' is referencing claim 21, lines 13-14.--
4.
The following is a quotation of 35 USC § 103 which forms the
basis for all obviousness rejections set forth in this Office action: A patent may not be obtained though the invention is no;t identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having> ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. Subject matter developed by another person, which qualifies as prior art only under subsection (f) or (g) of section 102 of this title, shall not preclude patentability under this section where the subject matter and the claimed invention were, at the time the invention was made, owned by the same person or subject to an obligation of assignment to the same person.
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-3-
5.
Claims 4-11 and 15-21 are rejected under 35 USC §103 as
being unpatentable over Baldwin et al. Baldwin teaches the invention (claims 4, 15 and 21) substantially as claimed, including a computer system and method for operation a memory cache apparatus, the system and method comprising: (a) a host microprocessor having a host address bus and a host data bus (e.g., see aol. 9, lines 39-52 and Figure 1); (b) an input register connected to the cache memory and the host data bus (e.g., see col. 50, lines 33-42); (a) a system memory having a system address bus and a system data bus (e.g., see Figures 34-37, 41); (d) a tri-port cache memory which essentially functions as a dual port cache memory and connects to a system bus and a host bus (e.g., see aol. 15, lines 45-62); and, (e) an input register connected to the dual port cache memory and the system data bus (e.g., see col. 67, line 47 to aol. 70, line 30). Baldwin does not specifically teach a cache controller connected to the dual port cache memory, however, functions performed by a cache controller are performed by the three processors connected to the data cache memory (e.g., see col. 15, line 17 to col. 16, line 11). It would have been obvious to one
of ordinary skill in the art of memory storage at the time the invention was made to equate the functions of the processor modules to the functions of a cache controller because the
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processor modules perform the data control and transfer tasks typically performed by a cache controller. As to claims 5 and 16-17, Baldwin teaches the host processor concurrently processing tasks with access the cache memory with the other processors of the system (e.g., see aol. 1, lines 29-52)
.
As to claim 6, Baldwin teaches the host data bus is asynchronous to the system data bus (e.g., see col. lines 38-41)
.
1,
As to claim 7, Baldwin teaches control sequencing of addresses and data signals (e.g., see col. 20, line 63 to col. 2,line 51). As to claim 8,1 Baldwin teaches local bus cycles (e.g., see aol. 15, lines 45-62)
.
As to claims 9 and 10, 'IBaldwin teaches a peripheral device coupled to the system which provides data to the cache (e.g., see aol. 16, lines 25-62).,_ As to claim 11, Baldwin teaches sub-systems operating at different parameters (e.g., see cal. 3, line 27 to col. 6, line 15). As to claims 18-20, Baldwin teaches data is rnoved to the cache to and from by the processors during clock cycles (e.g., see col. 15, line 15 to col. 16, line 24).
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6.
Any inquiry concerning this communication or earlier
communications from the examiner should be directed to Reba. I. Elmore whose telephone number is (703) 305-3819. .The examiner can normally be reached on Monday-Thursday from 6:30AM to 5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Tad R. Swann, can be reached on (703) 308-7791. is (703) 305-9565. Any inquiry of a general nature or relating to the status of this application should be directed to the Group receptionist whose telephone number is (703) 305-9600. The fax phone number for this Group
ReaI. Elmore Primary Examiner DecemTber 8, 1995
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EXHIBIT 19
Case 1:06-cv-00788-JJF
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it
'0
r
S*/
UNITEDýSTATESs *PARTMENT OF COMMERICE Patent and Trakiimark Office I
Address: COMMISSIONER OF PATENTS AND TRADEMARKS Washington, D.C. 20231
ATTORNEY DOCKET NO.
E
APPLICATION NUMBER
FILING DATE
FRST NZ.ED APPLICANT
Al
El"3MI / 0 1 6,'-
4Y1 D:D13C 10
El El
DA
EXMIE
EL.MORE, R
ART UNIT PAPER NUMBER
SKJERVEN,* MORRII-lL, FReINKI..IN & FR IEL SAN~k JOrCSE i.",A 9!5 110
MAlCPHIERSONM,
:w25 METRO DRIVE,* SUJITE 700
i
MIED
This isa communication from the examiner ihcharge o)fyour application. COMMISSIONER OF PATIENTS AND TRAOEMRKS1
*
on! a1N?esponsive to communication(s) filed t This action Is FINAL. hL
OFFICE ACTION SUMMARY ~5 c 7-
0,S)hftce this application is in condition tar a lowance except for,formal matters, proseution as to the merits Is'closed in accordance with the practice under Ex pjirte Quay,Id, 193 D.C. 11; 453 0.G. 21se.
*-A
month(s), or thirty days, shortenedr statutory period for response to Whs actioh issiet to expire--Lý whichever is loinger.p from'the mailing date of1this communication. Failure to respond within the period for response will cause 33). Extensions of time mnay be obtained under the provisions of 37- CFR the application to become abandoned. (35 V: .C.. 1 1.136(a). Disposition of Claims
Clalm(s)
q -t
____________________1___3_____Z___
is/ Iare pending in the application.
Of the above, clailm(s) ____________________________ El Claim'(s). ýN G(Iaim(s) 0i Claim(s)
'Is/are
is/are withdrawn from consideration. allowed.,
(~-L '-
S
3 -is/are
1'are
rejected. is/re objected to. subject to restriction or election requirement.
-
O- Claims
Application Papers
"I See the attached Notice of DraftspersonsPtn 'rwnleie,PO98
O The drawing(s) filetd on
[is/are
objected to by the Examiner. is El approved Ell. disapproved,
El The-proposed drawing correction, filed on El The specification is objected to by the Exarrinerl
Li
The oath or declaration is objected to by the Examiner.
Priority under 35- U.S.C. § 119
Li Acknowledgement is made of a claim for' foreign poiyunder 35 U1.<§I19(a)-(d).,
r l All El Some* El None of the CERTIFIEcpe ftepirt'ouet
sdpirt
aebe
ouet aebe
oisO Li received.,lt Li received in Applicati¶ No. (Series Code/SerialNumber) ELi receive Inthi *Certified copies not received:I
'Z4onal stage appIicýtion from? the International Bureau (PCT R,ule 17.2(a)),
EL Acknowledgement is Made of a claim for domesticipriority under 35 US.Q. §119(e).
Attachment(s)
LiNotice of Reference
Cited, PTO-892
7/4
vs
/
I~nformation Disclosure Statement(s), PTO-1449, Paper No(s). El Interview Summary, PTO-413 EL Notice of Draftsperson's Patent Drawing Review:, PTO-948
V
I
Li- Notice of Informal
PTOL-326 (Rev. 1WS)
Patent Application, PTO-1 52
-SEE
OFFICE ACTION ON THE FOLLOWING PAGES
-us GFO 1996-409 290140029
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1. 2.
Claims 4- 11 and 15-32 are presented for examination. The amendment filed 10- 17-96 does not meet requirements for the filing of amendments
to the claims under 37 CFR 1.21(b). After the claim number for an amended claim the applicant must state either the claim is amended or the number of times the claim is amended, such as: Claim 4. (amended) or Claim 4. (twice amended), whichever is applicable. 3. The rejection under 35 USC 112, second paragraph, is maintained since the submitted
amendment to claim 21 could not be entered. 4. 5. The rejection under 35 USC 103 is maintained. As to the remarks, Baldwin teaches the present invention to the extent claimed. A cache
memory is a fast memory element and without specific caching details appearing in the claims, any memory element, especially one designated by the reference as a cache is considered equivalent to a cache memory unless specific details of the claimed cache are present in the claims. The same is true for a processor which is chaimed as a 'host processor.' Without supporting limitations within the body of the claim requiring specifics of a host processor which read over the host processor of the prior art, the limitations are considered taught to the extent claimed. As to the input registers, the holding registers and output registers are taught to the extent claimed for claims 21 and 22. The rejection cites sections of the reference for claim 22 ans well as the other independent claims. 6. As the applicant amendment could not be entered, this office action will not be made final
at this time.I
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-3-
7.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Reba. 1. Elmore whose telephone number is (703) 305-3819. The examiner can normally be reached on Monday-Thursday from 6:30OAM to 5:00OPM. If attempts to reach the examiner by telephone are unsuccessKhl the examiner's supervisor, Tod R. Swann, can be reached on (703) 308-7791. The fax phone number for this Group is (703) 305-9565. Any inquiry of a general nature or relating to the status of this application should be directed to the Group receptionist whose telephone number is (703) 305-9600.
Reba 1.Elmnore Primary Examiner January 4, 1997
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EXHIBIT 20
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AI L-.\M\1018\2P\O\PAMD0.BNK(
PATENT
IN THE UNITED STATES PATENT AND TRADEMARK OfFIC,Tg_lL
Applicant:
Assignee: Title: Serial No.: Examiner:
Alfred K. Chanoc2
MOS Electronics, Inc. RANDOM ACCESS CACHE MEMORY CONTROLLER AND SYSTEM 07/678,914 Filed: April 1, 1991 233
Group Art Unit:
M-1018-2P US
Attorney Docket No.:
fpr
-5p1
San Jose, California October 18, 1991 COMMISSIONER OF PATENTS AND TRADEMARKS Washington, D. C. 20231 PRELIMINARY AMENDMENT Sir: Please amend the above-identified application tiled April 1, 1991 as follows.
IN THE CLAIMS Please add Claims 5-14 as-follows:
975.(New)
provides a second / first address co
The comp
er system as recited in Claim 4
ller provides a first address on said
wherein said cache cont
host address bus at t e same time said cache controller dress on said system address bus, said esponding to a different memory location than
said second add ess.
(New)
The computer system as recited in Claim
wherein data on said host data bus is asynchronous to data on said system data bus. (New) The computer systemlas recited inCli
wherein,said cache controller comprises: a first1control sequencer for controlling addressing
LAW
Mageosa,
6KJERVEIN;, MORR81t., MAC'8Z0SON _RILIN
a
FRtIEL.
SUITE 700 SAN JOSE, CA 9 1 10
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L:\M\1018\2P\O\PAMb .BNKCPTN
PATENT
and data signals on said host address bus and on said host data bus; and a second control sequencer for controlling addressing and data signals on said system address bus and on said system data bus.
5
(New)
The computer system as recited in Claim/
further comprising means for disabling said dual port cache memory during a local bus access cycle. (New) The computer system as recited inCli
further comprising a peripheral device coupled to said system memory. (New) The computer system as recited in Cam
wherein said peripheral device provides data to said system data bus, and wherein a hit address memory location within said dual port cache memory is loaded with said data from said peripheral device if the hit address of said dual port cache memory corresponds with an address of said data from said peripheral device.
11.
(Hew)
The c
puter system as recited in Claim 4
wherein said host micr processor operates at a first frequency, and wherein said syste memory operate's at a second frequency
that is different from said first frequency.
12.
(New)
The method
r oa ting a ca'che memory
/
apparatus as recited in Cl im
coupling said host port
ther compri.sing the step of
o saiFsytmport wh en a read miss
SK(JURVEN. MIORRIL.L, MkcPHERSON. FRANKLIN
& FRIEL
25 METRO
OR;VE
j
)
2-
S.1TE I00..
SAN JOUh. CA 95110J (408) 283-1222 , __FAX (4001 202-iflS
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PATENT
13.
(New)
The method f r operating a memory cache 1 wherein said cache memory
apparatus as recited in Clai
apparatus further comprises an update register for providing data from said system por to said random access memory, said
method comprising the fu ther step of loading update data. from said system port into aid up_ate register.
14.
(New)
The metho a-
fo
operating a memory cache 1 wherein said step of latching
apparatus as recit din
input data into s id input register from said host port occurs in a first cloc input data int clock cycle; cycle and wherein said step of loading said said random access memory occurs on a second aid second clock cycle immediately following said
first clock cycle.
REMARKS Applicant requests the Examiner to add Claims 5-14 as indicated above. Examination and allowance of the pending
claims is requested. Respectfully submitted,
B. No81 Kivlin Agent for Applicant Reg. No. 33,929
I hereby
certify that this correspondence is being deposited with the United States Postal Service as first class mail in an envelope
addressedto: Commissioner of Patent D.C., 2023 1, on _Z·Zb .
Date of.Signature
d Trademarks, Washington,
Aet
for Applicant
IA.
SAN~4 JOE
111..C
A 51
."
(40e)
29
%2
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EXHIBIT 21
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/
i
LAIMS\&55M lI8-2\QO63ýo9ANvI 930614 (spw)
TN THE uNITED STATP.S PATEPNT AND) TRADEMARK OFFICE 'Applicantt: Assignee: Alfred Chani MOS Electronics Corporation c.
/ýq
:11
ITitle:
Serial No.:
"RANDOM ACCESS CACHE MEMORY CONTROLL46AfiD C SYSTEM" 07/678,914 Elmore, R. Filed: 04/01/91 ý3i2 C_-
Examiner:
Group Art Unit:
Attorney Docket No.:
M-1O18-2P US
San Jose, California 'June 14, 1993 commissiONER OF PATENTS AND TRADEMARKS Washingtonj D. C. 20221 AMENDMENT Sir: Applicant submits the following amendments and remarks,in
response to the office Action dated January 14, 1993 in the
above-citbd case.
IN THE TITLE
-
Please amend the title of the invention to read:
II
tI-
"CONTROLLER FOR A RANDOM4 ACCESS DUJAL-PORT CACHE MEMORY SYSTEM".
_ __ _ _ _
Li 11__
I-
TN T11E.ABSTRACT Please amend the abstract as follows: Please delete numbered lines 20 through 29 of page 121.
IN THE SPECTFICATION Please amend the specification as follows: Page 17,1ftne -18, rewrite "hXdata" as --data--.
IN THE CLAIMS Please cahdel claims 1-3f and 12-14,withbut prejudice.
Plea§e amend the cLaims as follows:
SKJERVeN. MORRILL, MACPHERSON. FRANKLIN a FRIEL.
25 METRO DRIVE QUITE 700
FAX (400) 203.1233
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LA\DIVIS\5855WM-1018-2\006 3369.WP
9364.(pw
(Amended)
A
omputer system comprising:
*wc%Ja
host microp ocessor having a'host address bus and a
tivhost
data bus;
a system memo y having a system address bus and a
system data bus; a dual port ache memory having a system port
connected to said system data bus [and]. a host port connected to saidlhost data bus. said dual Port memory comprisincl a rand m access memory and a plurality of
t
____________
registers connectina said random access memory to said host port and saiR system port, wherein a data npath between said host
Jdata bus
and said system data bus is
decounled by said Irandom access memory and said nluralitv of registers; and a cache cont oiler connected to said cache mnemory. said cache contro ler having a first port connected to said host addressibus and a second Port connected to said
system address buEj.
4W455.
rovidin
#y[at
The corn uter system as recited in Claim 4 wherein
said cache control er is connected to said cache memory for [provide ] a first address on said host address bus
the] concurrent vwith providing [same time said cache ontroller provides) a second address on said system address us, said first addre s corresponding to a different memory location than said sec nd address.
W
SKJERVENl, MORRILL. MACPHERSON. FRANKLIN &FRIEL.
* Please add the following new claims:
15.
(New)
A
ethod for operating a memory cache
pparatus, said mem ry cache apparatus including a random ccess memory, a hos egister connected t port, a system,port, a host input said host port, a system input register
s?Yýtern output register onnected to said sy tern port, and -a.
2'I
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connected to said syste of:
port, said method comprising the steps
receiving an address from a host; comfparting,sa d received address to a plurality of addresses strdn said random access memory;
placing a li e of cache data from a location in said random access me ory into said system output register; placing dat register; wherein if said received address does not match one of said plurali y of cache addresses: placi g said host data into said location in said rando register; retri ving system data corresponding to said received ddress from said system port into said access memory from said host input from said host into said host input
system in ut register; and placing said system data corresponding to said received address from said system input register into said location in said random access memory, subsequent to said step of placing said host data into said random access memory, without overwriting said host ata.
2/
(New)
The method
y operating a cache memory further comprising the step
apparatus as recited in c-la'm)
of placing subsequent host data into said host input register concurrently with said st p of placing a line of cache data.
17.
(New)
The method for operating a cache memory
apparatus as recited in claim 15, wherein data from a plurality of data locations of aid randomt access memory are placed in
said system output re ister during 4 single clock cycle.
SUE~RVEN. M4ORRILL, MACPHERSON. FRANKLIN
R FRtIEL.
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Z
(New)
The method for operating a cache memory further comprising the step
apparatus as recited in claim,,
of coupling said host port to said system port when a read miss cycle occurs.
19.
(New)
Th
method for operating a memory cache in claim 15, wherein said step of placing
apparatus as recite
data from said host into said host input register occurs in a first clock cycle, nd wherein said step of placing said host
data into said loca ion in said random access memory occurs on a second clock cycl foqllowing said fir
,
said second clock cycle immediately clock cycle.
(New)
A computer system according to claim
wherein
34
said dual port cache memory comprises a plurality of burst random access memories.
21.
(New)
A comput r system comprising:
a host micropro essor having a host address bus and a host data bus for pr viding a host address and host data;
9.-,
U,
a system memor
for storing system data, said system
memory having a sys em data bus for providing system data; a dual port ca he memory for storing said host data and system data; a host input r gister connected to said dual port cache memory and s id host data bus for providing data from said host dat bus to said dual port cache memory;
a system outp t register connected to said dual port cache memory and s id system data bus for receiving a line of cache data fro said dual port cache memory and
providing said 11 e of cache data to said system data bus; a controller connected to said dual port cache memory and said host ad
SUJERVEN, MORRILL. MACPHERSON. FRANKLIN &FRIEL
2 .ME.O'CV SUtTE 700 SAom~ A 0
ess bus, saidi controller containing a
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plurality of addresses for receiving said host address from said host addres bus and comparing said host address
to said plurality of addresses; wherein when a atch results from said comparing:
host data from said host input register is
2)
5'
placed into s id dual port cache memory at a location of said line system f cache data; and ata from said system input register is
placed into said location of said line of cache data after said ost data is placed into said dual port
cache memo y, wherein said host data is not overwritte.
1--I 4
/
I
REMARKS
These remarks are in response to the Office Action dated January 14, 1993, which has a shortened statutory period set to A two-month extension, to expire June
expire April 14, 1993.
14, 1993, is requested in a petition filed herewith. Claims 1-14 are pending and rejected under 35 U.S.C. S 112 and over prior art. Claims 4, and 5 are amended. Claims 15-2 1 are added. Claims 1-3 Claims 1-
are rewritten for clarity. 3, and 12-14 are canceled.
Reconsideration is requested.
The specification is amended for clarity.I The Examiner has objected to the title of the invention. This rejection is overcome by the above amendment to the title. The Examiner has objected to the abstract.' Applicant has amended the abstract to overcome this rejection. The Examiner has objected to the disclosure for the reason that the claims are not presented in a "preferred format". Applicant traverses the objection on the grounds that (1) line numbering for the claims have been presented in the conventional page line numbering format; and (2) no requirement as made by the Examiner is known in the PTO rules.
SKJER~VEN. MORRILL, MAACPHERSON. FRANKLIN a,rRIEU.
-SUITE SAN JOSE 700 CA 95110
-5 -
4084)ý. 2812C FAX((400) 283-1233
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With regard to small entity status, the Assignee's attorneys have reviewed M.P.E.P. S 509.03 and withdraw the request for a determination by the office on this issue. The
facts stated in the letter dated March 10, 1992 in this case are, however, before the office, and if the office has any reason to believe that at the time of filing this case was not entitled to small entity status, the office should so inform Applicant.
Rejections under 135 U.S.C. q 112 Claims 1-14 were rejected under 35 U.S.C. § 112, second paragraph. The Examiner has written:
It is unclear as to where the plurality of cache addresses are stored and as to how a comparison is achieved in claim 1. claim 1 is rewritten for clarity as new claim 15, which recites
"..a
plurality of addresses stored in said random
t access memory; ...'1, as supported in the specification on page
12, lines 2-10, and generally throughout.
Address comparison
techniques are well known in the art of cache memory management. See, e.g., Intel Corporation, "Ii486 Microprocessor
-
Hardware Manual", pp. 6-1
6-11, 1990,ia copy of which is
submitted in an accompanying Information Disclosure Statement. Applicant need not recite this process in a claim, since it is not believed essential to novelty. See M.P.E.P. 706.03(f).
New claim 15 overcomes the Examiner's rejections to claim 1 under 35 U.S.C. S 112. The Examiner writes: It is unclear as to what is actually occurring in the step of "providing said replaced data to said system port" because making the data available to a port does,not appear to be a constructive step... This rejection applies to method claims 1-3 and 12-13. This rejection is overcome by the new claims. Applicant
maintains that "providing data" is a constructive step in that
it
SKJERVEN. MORRILL,
MAcPHERSON. FRANKLIN & FRIEL
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enables subsequent functions to occur which are conditional
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on the presence of the data. Claim 5 has been amended for clarity and overcomes the Examiner's rejection thereto under 35 U.S.C. S 112. The Examiner writes: It is unclear in claim 10 as to why data must be loaded from a peripheral device when the claim states there is a'hit condition in the dual port cache memory. As supported in the specification, pages 104 to 106, hits in the cache memory may also be registered by devices other than the CPU. System memory data which has been manipulated by
other devices must update the cache, so that the CPU has access to the most recent copy of data. respectfully traversed. Claim 13 is canceled, thereby obviating the Examiner's rejections thereto. For the above reasons, Applicant requests reconsideration and withdrawal of the rejections under 35 U.S.C. S 112. This rejection is therefore
Prior Art Relections The Examiner rejected claims 1-8 and 11-14 under 35 U.S.C. §102(b) as being anticipated by Thomas et al. writes: Thomas teaches the invention (claim 4) as claimed, including a computer system comprising: (a) a processor (e.g., see Figure 1); (b) a system memory (e.g., see Figure 1); (c) a dual port cache (e.g., see Figure 1); (d) a cache controller (e.g., see Figure 1); Figure 1 of Thomas et al. shows an output bus 25 from cache 15 coupled to CPU data bus 38. hits to CPU 12. memory unit 18. Bus 25 supplies cache The Examiner
Bus 38 returns move-in data from mainstore In the event of read hits following a miss,
move-in data along bus 38 will contend with CPU reads of the cache along bus 25. Data from both buses cannot traverse one
line to the CPU simultaneously since the data paths are coupled.
SKJERlfEN. MORRILL, MACPHERSON. FRANKLIN7 *&FRIEL.
SUITE 700 SA.
Therefore, cache read hit, processing cannot occur
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during the cache update required by the previous miss. In contrast, claim 4 as amended recites:, said dual port memory comprising a random access memory ... and a plurality of registers connecting said random access memory to said host port and said system port, wherein a data path between said host data bus and said system data bus is decoupled by said random access memory and said (Emphasis added). Plurality of registers... Support for claim 4 is shown in Applicant's Figure 8 (elements 106, 108, 114A-D, 116A-D, 118A-D, 112 and 113)
.
The
specification teaches decoupling of host and system data buses on page 6, lines 20-25, page 115, beginning at line 31 through page 116, line 5. Thomas et al. does not disclose or suggest
the structure recited in claim 4. The structure of claim 4 advantageously provides faster execution by enabling system fetch completion during subsequent
CPU read and write cycles, as disclosed on page 61 of the
specification, lines 22-34, with reference to Figure 24. 4 therefore distinguishes over Thomas et al. The Examiner writes:
- Method claims 1-3 and 13-14 do not teach or define over the above rejected apparatus claims and are rejected on the same basis.
Claim
Thomas et al. does not disclose transfer of memory between a CPU, a cache memory and a system memory such as would occur during a write miss operation. A write miss operation
requiring cache update in the system of Thomas et al. requires either: a CPU write to system memory before moving-in the data from the requested write address, or that the CPU wait until the requested data is moved-in from mainstore memory to the cache memory before updating the cache. In either case, a slow
mainstore access is required before the CPU can continue execution, undesirably slowing performance. Therefore, in contrast to Thomas et al., new claim 15 (replacing claim 1) recites: .. placing said system data corresponding to said received address from said system input register into
SKJERVEN. MORRILL,
MAcPHERSON. FRANKLIN
& FR4IEL
25SMETRO DRIVE SUITE 700
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said location in said random access memory subsequent to said step of placing said host data into said random access memory without overwriting said host (Emphasis added). data... support for new claim 15 is found at page 58 of Applicant's specification, lines 5-12. The method of new claim
15 advantageously provides a faster write miss operation by allowing the CPU to write to the cache immediately and resume execution without waiting for system data to update the cache line. The placing step as recited in new claim 15 is not
disclosed or suggested in Thomas et al. Thomas et al. does not disclose any details of cache updating. Thus move-in operations in Thomas et al. will
apparently overwrite all previously written cache data at a cache location, and hence claim 15 distinguishes thereover for the additional reason that claim 15 recites "without overwriting". Claim 15 therefore distinguishes over Thomas et al. for at least the reasons stated above.
Rejections under 35 U.S.C. S 103 Claims 9 and 10 are rejected under 35 U.S.C. S 103 as being unpatentable over Thomas et al. Insofar as claim 4 is distinguished.over Thomas et al., claims 9 and 10 are likewise distinguished by at least their dependence from claim 4. Applicant requests reconsideration and withdrawal of the rejections under 35 U.S.C. S 103.
Claims 2, 3, 12 and 14 have been canceled and rewritten for clarity as new claims 16, 17, 18 and 19, which respectively recite the limitations of originally filed claims 2, 3, 12 and 14. No new matter is added. New claim 20 is supported at page 12 of the specification,
SKJERVeN. MORRILL. MACPFIERSON. FRANKLIN9 & FRIEL. SUITES 700
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