Free Redacted Document - District Court of Delaware - Delaware

Case 1:04-cv-01371-JJF

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Case 1:04-cv-01371-JJF

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United States Patent
mthmd

1191

Ill] Patent Number:
(451

4,811,075
Mar. 7, 1989

Date of Patent:

HIGH VOLTAGE MOS TRANSiSTORS Invat011 glas H Eklm4 Los Gates, Calif. .
Assignee:

Aaincmt Examiner-Jerome Jackson A m e y , Agent, or Finn-Thomas E Schatzel

Power Wegmthns, lnc., Mountain

ve , Calif. iw AppL No.: 4 . 9 l94 File& Apr. 24 1987 Znt U' -.., ........ HOlL la HOlL 29/78; . .-. 7 HOlL 29/80 US. C. .., l ,-. .. ..-..-. 357/46: 357/22; 357n3.4; 357m.8 Field of Surd .,. "-....... 357/23.8.23.4,46, ... 357m
Ref-= ctd ie U.SPATENT DOCUMENTS
4,626,879 1U1986 c . r -.-,-,, d) 4 6 0 3 1 1U1986 Tbomar ..---.,2,4

357n3.8 357n3.8

OTHER PUBLICATIONS
S~G Phgsics

of ~mkvnductmM

u Wiley & Sons

N Y c 1981 pp. 431438.486491. ..
Primorg Examiner-Andrew

An insulated-gate, field-effect transistor and a doublcsided, junction-gate field-elfect tram-ktor are connected kt series on the same chip to form a high-voltage MOS transistor-An extended drain region i f o n n d on top of s a substrate of opposite conductivity-typematerial. A top layet of material having r conductivity-type opposite that of the exteaded drain and similar to that of the substrate i provided by ion-implantation through the s same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which Iias en& contacting a silicon dioxide layer thereabove. The tor, layer i either cons nectcd to the substrate or left flbat&g. Current f o lw through the extended drain region can bc controlled by the substrate and the top laya, which act as g a t e providing &I* for pinching oathe -ded drain region thurbetweea A complementary pair of such high-voltage MOS transistors having opposite conducti6ty-type are the same ,-hip.
7 C h h , 2 Drawing Sheets

J. Jama

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Patent

MS~. 7,1989

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4,811,075

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US. Patent

MW.7,1989

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Case 1:04-cv-01371-JJF

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neath the gate to a pocket 38 located beneath the dnin atended drain region therebetween. Thus, the transis- contact 32, and the extended drain region continues a similar distance on the opposite side o the drain f tor 1 can be conderal as an insulated gate. field-effect @ -tor (IGFET or MOSFET) connected in series cantact. A top layer 39 of n-material is provided by with a doubleaided,junction-gate fieldeffect transistor 5 ion-implantation through the same window of the mask w e the iasulated gate, field-cffed tramisor as the extended Qain region to c o v a an -lntennediate shown ir a c o n v a t i o d MOS type, it should be nndcrportion them£ The end portions of the extended drain stood th.t it could also be a lateral DMOS ar a deplerh e g an uncowed so as to contact the silicon dioxide layer I .The top layer i either connectedto the n-well Z ~MOStypr By adding the top layer 27 over the extended drain 10 or left hating. region 26 d connecting this top l a p to the substrate The gate 34 controls by ticldzffect the current flow thueunda latenlly through the =type material to the 11, the net number of charges in the extended drain region can be iocnasal from 1X 1012/cd to around py e material in the extended drain region37. Further tp flow h g b th udended drain region can be conZX 1012/cm2, o approximately donbk This drastically r reduces the on.rc&ancc oftbe tradstor 10. The pinch I trolled by the n-well33 and the top layer 39, which a t S c off voltage of the uteaded drain region can be reduced gates providing tield-effeds for pinching off the orfrom typically vaYad forty volts to bdow ten volts. tended drain r e d m &erebetween Thns, the -or n s a c~lventionalshort cham4 thin gate oxide 30 cSn be w nd r d as an insulated-gate fiekhffect u, n i ce MOS trrurdstors can be wed as the series hanshtor trrdstor (IOFET o MOSFET) connected in series r butad of a DMOS device. Thi,reJults in t h follow- 20 *pith a doubhidcd, jaactiongte field-effect transistor iqg kndk F R the threshold voltage of a convmU The n-well undathe artendcd drain regionhas tional MOS k u d t o r is typically much lower than for t be depleted M r breakdown occurs between the o oe a DMOS device (0.7 volts compared to two four volts p+ drain contact pockc! 38 and the n-wdl for the D-MOS device) and thus, b d u d y compahiIe ~ooling now at FIG. 3 an nchaancl traasinor 1 , , 0 with five volt logic. Tbe D-MOS device h 1 y re- 25 dm& to t a shown in FIG. l and a pcbannel transisht , quira an dditioad power supply of ten to *en volts tor 30. similar to that shown L FIG. 2, are shown as a fix driving the gate Second, the conventional MOS comp~ancntlry on the same substrate 1 and is+ pair 1 tnnsbtor hu less on resistance and thus, further relrted fromeach other. S i the details of eacb eansisdncu the totai on redstaoce. tor has been previously described with reference to As the p-typc top layer 27 can be made very shallow 3 FIGS. 1 and 5 no farther dacription is considered 0 with a depth of one micron or less, the doping dmsity in necessary. tbat laya will b m thc range of 5 X IOlLl X 1017/cm3. e As sbown i Fla. 4, low voltage, CMOS implo n At doping kvek above 1016/cm3, the mobility s a t to trs mated devices43 and 44 can be combined on tiu same dtgrode and a decrease in m b l t will increase the oiiy pabmite 1 as the high voltage devices 10 and 30, 1 c i i a elecbical field for breakdown, thus giving a 35 shownm F G 3 'Ihw low voltage devices enable low rtcl I. . higher breakdown voltage for f e geometry. The ud voltage logic and aaalog hmction to control the high number of charges in the top l a y a is around voltage devices The device 43 is an n-cbannel type 1X 1012/cm2 and to Iirst order approximation indepenhaving a so amtact 46, a drain contact 47 and a dent of depth. polysilicon gate 48. A p+ pocket 49 and an n+ pocket The combined benefits of the above fcaturu result in 40 51 are provided m the p- substrate bmeath rhe source a voltage capability of three hundred volts w t a figure contact. Then+ pocket extends to beneath the gate An ih of merit. R, x A, of about 2.0 R m d for the transistor n+ pocket 52 is provided beneath the drain contact. Thc 1 . Currently mcd integrated MOS transiston have a 0 gate 48 is insulated from the sabstme by the silicon t l p r e of m r t of about 10-15 0 m d , while the best ei dioxide layer 1 ,but the gate colltrok the nvrent now 2 discrete vertical D-MOS devices on the market in a 45 through tbe substrate betwcen pockets 51 and S . The Z M u voltage m g e have a t3gtu-e of merit of 1-4 t 3 gate is covered by the insulation Layer 18. An n-weU 53 mz. h provided in the substrate to accommodate the low W~threference to FIG. 2, a p - c h a d type, hi& voltage. p-channcl device 44. This &vice incl& a voltage MOS trrnsisror h bdbtcd generally by refersource contact 54. a drain contact 56 and a plysilicon a c e numeral 3 . S i the layas of substrate. silicon U) gatc SI. An n+ pocka 58 and a p+ w e t 59 an pro0 dioxide, and halation for this traasirtor are similar to vided in the n-well beneath the source contact and a p+ t b a a previously d e x n k d for transistor 10,they will be pocket 61 b provided in the n-well beneath the dnin &aEke reference numaak A pubstrate 1 h cov1 contact. The gate 57 is indated hrw the n-wd and era3 by a silicon dioxide layer U and an hulation layer extends thereabove between pockets SO and 61. 18. A metal sours contact 31and a metal draiu contact U It should be noted that the t a m "snbmten refen to 32 extend thmngh tbe insolation layer and the silicon the physical material on which r microcircuit is fabridioxide layer to an *well 33 that is embedded in the cated. Ifa transistor is fabricated on a well of n or p type substrate A polysilicon gate 34, which is an electmdc. material within a primary substrate of opposite type i positioned between the source contact and the drain s material. the well material can be considered a secondcontact at a location whnt the silicon dioxide layer is 60 ary substrate. Similarly,ifa transistork f a b r i d on an very thin so that the gate is slightly offset and insulated epitaxial layer or spi-iiand that merely supports and from the n-wdl The gate and the silicon dioxide layer insulata the t n m s h r , the epitaxial layer or epi-island are covered by the insulation layer 18. can be considered a secondary substrate. An epi-island A pockcf 35 of n+ type material and a pocket 36 of b a portion of an epitaxial l a y a of one condoctivity p+ type material are provided in the n-well33 beneath 63 type that is isolated from the remainhrg portion of the the metal source contact 31. The pocket 36 extends to epitaxial layer by didusion pocketa of an o p m t e conthe gate 34. An extended drain region 37 of ptype ductivity type. When c o m p b t a r y lra~sistorsarc material is formed in the n-well and extends from beformed on the same chip, the well in which o a t compliP C as gates providing fidd-effects for pinching off the ~

3

4,811,075

4

( . m

(m.

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