Free Redacted Document - District Court of Delaware - Delaware

Case 1:04-cv-01371-JJF

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United States Patent
Balakrishnan et al.
FREQUENCY JInERING CONTROL FOR VARYING THE SWITCHING FREQUENCY O F A POWER SUPPLY
both of Saratoga; Lei1 Lund, San Jose, all of CA (US)

(10) (45)

Patent NO.: US 6,249,876 ~1 Date of Patent: Jun. 19,2001

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(75) Inventors: Balu Balakrlsbnan; Alex Djenguerian,

Ashok Bidra, "Power-Conversion Chip C t Energy Wastus age in Off-Line Switcbers," Electronic Design, pp. 46.48, Oct. 1998. cited by examioer

(73)

Assignee: Power Integrations, l a c , San Jose, CA (US) Subject to any disclaimer, the term of this patent is extended or adjusted under 35 US.C. 154@) by 0 days.

Primary Exminer--Dennis M. Buder (74) Anwney, Agent, or Firm--Blakely, Sokoloff, Taylor & Zafman, LLP.
(57) ABSTRACT

( ) Notice:

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Appl. No.: 091192,959 Filed: NOV. 16, 1998

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(9) Lot. CL7 G06P U04 (52) US. C1. ........................... 7131501; 713/300; 7131503 (58) Field of Search 7131300, 320, 713/322,500, 501,503
(56)

References Cited

U.S. PAENT DOCUMENTS
4,712,169 * 1211987 Albach 4,930,%3 5/1990 fbmc e3 al. 5,459,392 * 1011995 Mancklcoro
6,107,851

*

33 6m 363P1 3231222
321/172

EM1 emission is reduced by jittering tbe switching frequency of a switched mode power supply.An oxillator with a conlrol input for varying the oscillator's switching f n quency generates a jittered clock signal. lo one embodirncnt, Ibe oscillator is connected to a counter clocked by the oscillator. Tbe counter drives a digital to analog converter, whose output is connected to the control input of the oscillator for varying the oscihtion frequency. In another embodiment, the oscillator is wnnected to a low frequency s oscillator whwc low frequency output i used to supplement the oulput of the oscillator for jittering the switching frequency. Tbe invention thus deviates or jitters the swilching frequency of tbc switched mode power supply oscillator within a narrow range to rcducc EM1 noise by spreading the energy over a wider frequency range than the bandwidth measured by the EM1 test equipment.

8ROIX)

Balakinhnan et at.

32 Clalms, 6 Drawing Sheets

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US 6,249,876 B1
1
FREQUENCY JI1TEIUNG CONTROL M)R

2
frequency jittering circuit varies tbe switching frequency using an oscillator for generating a &tching frequency signal the oscillator having a control input for varying the switching frequency. A digital to analog couverter i s con5 nccted to the control input for varying the switching frt9ue"y. and a counter is con=led to the output of the oscillator and to the digital to analog convener. Tbe counter causes the digital to analog wnvcrter to adjust thc control and to the swi'c"i~g Irequency. lmpkmcntations of the invcntion inch& one o r more of lo the following. ' oscillator bas a primary current source k con~ected 10 the oscillator control input. A differential switch may bc used wih first and second tmnsisfors connected 10 the primary current smrce; a third transistor IS connected 1 the &st transistor, and a fourth transistor 0 connected to the %mod transistor at a junction. A capacitor a d 0 or more comparators may be connected (0 the " junction. Ihe digital to analog converter bas one or more -nt sources, with a tramistor connected to each current 20 and to counter. The primary may gene"1~ 1 -01 I and each of Lbe cuncnt sources may generak a current lower than I. The current souroes may gcmrale binary weighted currents. The largest cuncnt source may generate a current which is less than about 0.1 25 of I. In a a s p q a metbod for generating a switching frt9uenc~ a power conversion system includesgenerating in a primary currenS cycling o w o more secondary current r 10 generate a secondary -nt which varies over 30 lime; and suPF'l~ingthe primary a d secondary currents to a control input of an oscillator for gemrating a suritcbing is varied Over lime. 'quency lmpkmentaiiom of the invention include one or more of the followiog. A counter may be clocked with the output of 35 the oscillator. The primary current may be genenled by a cumof source. If the primary current i I, each of the s ~ w n d m ~ current sources may generate a supplemental cumnt lower than I and which is passed to the oscillator C O ~ ~i O I . ' h e supplemental current may be binaryW1 40 weighted. largest supplemental current may be less than I. aPProximately In another ksped. a method for gemrating a SwiIchiug f r q ~ e n c y a power couversion system iocludesgeueratiog in 45 a primary VolWe; cycling o m or more secondary voltage sources to generate a secondary voltage which varies over lime; and ~ p p l y h g primary and secondary vohages to the a control input of a v~ltage-controlledoscillator for generathg a switching frequency which is varied over time. lrnpkwntatiom of the invention include one or more of so the following. Where tbe primuy voltage is V each of the , " n d a r y v o b g c ~ ~ u r c may generate a suppiemental es voltage lower than V which may be passed 10 the voltagecoot10Ued OS~illato~. The supplemental voltage may be 55 binx~-wcigbtcd. In another aspecf a frequency jittering circuit for varying a power supply switching frequency includa an oscillator for generating a switching frequency signal, the oscillator having a control input for varying the switching frequency; 60 and means conocctcd to the control input for varying the switching frcque~cy. implementations of the invention include one or more of the following. The means for varying the fresucncy may . - . include one or more current sources connected to the control 65 input; and a counter connected to the output of the oscillator and to the one or more current sources. The oscillator mav include a primary current source mnoected to the control

VARYING THE SWITCHING FREQUENCY OF A POWER SUPPLY
BACKGROUND

Thc present invention relates to an off-line switched mode
control syslem with frequency jittering. M~~~ producls rely on elcccronic compoacnls to cost-effectively provj& the product with tbc dcsind fuoctionality. These electronic components require power regulation circuitry lo supply them with a clean and sfcady power of power. ne development of switched supply techwlogy has led to power supplies operating at high frequency to achieve small size and high e5ciency. Each switched mode power supply typically relies on an oscillator switchiag at a h e d switching frequency or alternatively a variable frequency (such as in a ringing choke power supply). D , , ~ to high fiequcncy relative to k q n e o c y of an alternating c u m n t (AC) power line, mode power supplies can cxaccrba[e probkms associaed cledromagne~c interference (EMI). EM] noisc is generated wheu voltage and current modulated by the switchiog power supply. hi^ electrical nois can be tramfcrrcd to the AC power line. In addition to affecting the operation of otber electronics e r h i n he vicinity of the power supply by conduction, EM] indued no& on a power l h e may radiate of kak from the power line and affect equipment which is w t even co-cted to rhe power lioe. Both oonducted a d radiated electrical noise may adversely affect or interfere with the operation of the electronic equipment. For example, EM1 noise generated by the switching power supply can taus problems for commmicatiou &vices in the vicioity of the power supply. Radiated high frequency noise components may become a part of the AC maim signal and may be provided to otber devices in the power grid. Further, power supply radiated EM1 can interfere with radio and television ~ra-issions. To a d d r w EM1 related interfere-. seven1 specifications have been developed by gover-nt in the United States and in the European Community. Thcse agencies have established specifications that define the maximum amount of EM1 that can be produced by various claof elcdmnic devices. S- power supplies geoerale a major i component of the EM1 for electronic &, ul important step in designing such supplies that conform to tbc specifications is to minimize EM1 emission to the -ptable limits of the variou specitications. EM1 may be r e d u d in a power a p p l y by adding snubbers and input filters. These components r e d u a the o noise rans sf erred l tbc power line and by so doing, also redua the clec~ric magnetic fields of noise generated by and the power tine. While thcst methods can redwe EMI, they usually complicate the design process as well as increase the production cosl. In practice, noise filkring componenls are added in an ad hoc manner and on a trial-aod-error basis during the final design process wheu EM1 i found to exceed s the compliance limits specified by the regulatory agencies. This inevitably ad& uuexpected cosls to the products. Further, e a r a components can undesirably increase the sire and weight of the power supply and thus the resulting product SUMMARY OF THE INVENTION EM1 emission is reduced by jittering the switching frcquency of a switched mode power supply. lo one aspect, a

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input; and a differential switch connected to the primary a capacitor in a low frequency oscillator. Further, the invencurrent source. The differential switch may have first and tion minimizes effects causcd by leakage cunent from second tramistors c o n w e d to the p r i m ~ y current source; transistors and capacitors associated with a low frequency a third tramistor connected to tbe 6rst tramislor, and a founh oscillator. n u s , the jittering can be transistor comeded to the second tramistor at a junction. A 5 even at high temperaturewhich can incnase leakage. capacitor and a comparator may be connected to the jnncAdditionally, the invention reduas the need to add extra tioe If the primary current source generates a each filtering comPownts associated with the EM1 filler. of the current sour- may pnerate a d -nt lower Therefore a inex~emive power than & cwrent 1, fufiber comp&ing a &amistor connected emissiom. to each current soura connccled to the cwnter. Tbe means . . be built for varying the frequency may ioclude one or more voltage '" BRIEF DESCRIPTlON OF THE DRAWINGS sources wnaected to the control input; and a counter connccted to the output of h oscillator and to the one or more e FIG. 1 is a schematic diagram of a digital frequeocy jiflering device. voltage souras. Tbe oscillator may include a primary voltage source connected to control ~ P U and a difkrential C FIG.2 is a plot illustrating the operation of the device of switch connected lo the primary voltage source. Tbc means FIG -. . 1 for varying the frequency may k1uk-a capacitor; a current FIG. 3 is a schmatic dirgam of an ambg frequency soar= adapted to charge the capacitor; and means for jittering devifc, altematingly charging and discharging the capacitor. One or FlG. 4 is a schematicdiagram of an implementltion of the more wmpmtorsmay be wnocctcd to flpacitor the of FIG. 3 . means for allernatinglycharging and discbargiogthe capaciFIG. 5 is a timine diagram illustrating the operation of the Inr. frquency jitter deha FIG. 4 . In yet another aspect, a power supply includes a FIG. 6 is a schematic diagram of a switched mode Power transformer, an ascillator for generating a signal having a frequency, Lbc oscillator having a control input for varying 25 supply in accordance with the present invention the frequeocy of the signal, the oscillator including a priDESCRIPTION mary current soura connected to the control inpur; a differential switch wnncded to the primary cumnl souroe; a FIG. 1shows a digital frequency jittering circuit 100.The capacitor conoected to the differential switcb; and a comdigital frequency jittering circuit 108 has a primary oscillaparator connected to b e differential switch. The power tor 110 which provides a clock signal to a arunter 140.Tbe supply also includes a digital to analog converter connected l primary oscillator l 0 typically operates between 100 kHz to the awtml input, the aoalog to digital cooverter having and 130 kHz. Tbe counter 140 can be a seven bit counter. one or more cunent souras, wherein the primary current Each ouwut of counter 140, when clocked by primary sour= generates a current I and each of the current sourcxs oscillator UO, represents a particular time interval. The generates a current lower than 1. A counter is connected lo ,5 outputs of the counter 140 are pmvided to a series of the output of Lhc oscillator and to b e current sources of the frequency jittering current sources 150.The outputs of the digital to analog converter. Further. a power tramistor is serics of frequency jittering current sources 150 are preconnected to the primary winding of L e transformer so that sented to the primary oscillator l l 0 to vary iis frequency, as will be described below. when the power transislor is modulated. a regulated power supply output is provided. Primary oscillator 110 contains a primary current source 40 In another Gpect, a power supply includes a transformer 122 which pmvidcs a primary current (denoted as 1) to node connected to an input vollage. n e power supply includcs an 123. Current 125 to the node W is providcd to the source, oscillator for generating a signal baving a frequeocy, the of MOSFETtnasis~ors and 132.'Zbe drain of MOSFET 126 oscillator having a control input for varying the frequency of transistor 126 is connected to the drain of an n-chamel the signal, the oscillalor including: a primary current source 45 MOSFET lraosistor la. Thc source of transistor U8 is connected to the control inpuS a differential switch congrouoded, wfik the gate of the tramistor 128 is comected nccted to the primary current source; a capacitor wnoected lo i s drain. The gate of the trursktor 128 is abo mnncded to the differential switch; and a wmparalor wnnected to the lo thc gate of an nchannel MOSFET tramistor 130. Thc diierential switch. A circuit for varying the frequency is source of the transistor 130 is grounded while the drain is connected to the m n t d input, the circuit having a capacitor; 50 connected to the drain of the MOSFET transistor 0 2 at a a current soura adapted to charge and discharge the capacinode 131.Transistors 126,128, U O and 132 form a differtor; onc or more comparators comecled to the capacitor to ential switch. The output of comparator 136 is connected to the current source for altermatingly charging a d discharging the gate of the transistor 132 and to an inverter lt4. The the capacitor. Further, a power transistor is wnnected to the output of inverter 124 is oonmcted to the gate of transistor oscillalor and lo the primary winding. The power transistor 55 126.Tbe comparator 136 has an input which is conneded to modulates ils output in providing a regulated power supply node 131 and to a capacitor 134. In combination, the output. Iransistors 126, 128, 130 and W2, capacitor 134. inverter Advantages of the invention include one or more of thc 124,current source 122 and comparator 136 form an oscillator. The output of the comparator 136 is provided as an following. The jitlering operation smears the switching frequency of the power supply over a wide frequency range 60 oscillator output OSC-OUT 101 and is also used to drive and thus spreads energy outside of the bandwidth measureti the clock input of counter 140. by the EM1 memrement equipment. BY changing the Countw 140hasa plurality of outputs QL-Q3(notsbown) oscillator frequeocy back and forth, the average noise meawhich are not used. The remaining outputs 04-07 are s u r d by tbe EM1 measurement equipment i reduced cons connected to a digital-to-analog (D-to-A) converter 150, sidcrably. 65 which may be implemented as a seriesof frequency jittering voltage sources or current sources. A Q4 output 155 is Further, the invention provides the required jittering without requiring a large area on the regulator chip to implerner~l connected to the gate of a p-channel MOSFET transistor

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US 6,249,876 B1
5
154. A Q5 outpull57 is connected to the gate of a pchanocl MOSFET transistor 158. The Q6 output 163 is connected to the gate of a p-channel MOSFET transistor 162, and 0 7 output 167 is connected to the gate of a p-channcl MOSFET tramistor 166. When D-to-A converter 150 is viewed as a 5 plurality of current souras, tbe source of transistor 154 is connected to a jittering current Source 152, which provides a current which i s Moolb of thc current I g e m a t 4 by current source 122. Thc source of MOSFET tramistor 158 is cmnecled lo a current source 156 which provides a current 10 sour= of the MOSFET that is %mth of the current 1. tramistor 162 is connected to a jittering current source 160 which provides a current that is %& FinaUy, t h c s o u ~ ~ 'of I. of the MOSFET transistor 166 is connected to a jittering -nt SJurce 164 which provides 1 Cumnt that i *tb of 1s s the current 1. 152,156,160 164 are bioary-weighted, that is, the current source 164 prov*s twice the current provided by the current source 160. Ihe ~ ~ s m r n 1 %tprovides t w i a the current suppkd by a 1 the a m c n t wurm 156 and the current source 156 p ~ i & sm twice the current provided by the current source 152. Further, in one embodimenl, the largesl current source current I provided 164 may supply no more than 10%of source 122. drain of t n k s l o r s by h e primary 154. 158. 162 and 166 are joined together such that the 25 suppkmenlal frequency jittering current sources of the D-10-A converter 150 c m be provided to su~piementthe primary current s o u r a 122. During operation, at every eight clock cycks, the counter output 9 4 on b e 1.55 changes slate. Similarly, at cveV 1 6 clock cycles, the output Q5 on line 157 changes state and at 163 changes every 32 clock cyck% the outPulQ6 on state, and every 64 clock cycles, the MtPut Q7 on line 167 changes slate. The entire counting cycle tbereafter repeats 35 itself. Each time the output Q4 on line 155 is low, transislor 154 is turned on to inject current in the amount of 11200 lo node I23 s o that the total current 125 is 1.0051. Similarly, each time that the output 0 5 on line 157 is low, tramistor 158 is 40 turned on to inject current in the amaunt of 11100to node 123 so that tbc lotal current 125 is 1.011. Further, each rime that output Q6 on line. 163 is low, transislor 162 is turned on to inject current in the amount of 1/50 10 node l23 s o that the total current 125 is 1.021. Finally, cach time that the output 45 Q7 on line 167 is low, the transistor 166 is turned on 10 ioject current i the unoun' of 1/25 to node 123 s o that the total n clurent 125 is 1.041. Additionally, when combinations of outputs 0 4 - 4 7 are turned on. lhe outputs of the respective curreot sources 152. 50 156,160 and 164 are added to the output of current source 122 to vary tbc frequency of the primary oscillator ll0. In this manner,counter 140drivc.s apluraliry of current souras to inject additional current to the main current s o u r a 122 such that the frequency of the primary oscillator 110 i 5s s varied. The jiltering operation of the embodiment of FIG. 1 is further illustrated in a chart in FIG. 2. A normalized operating frequency is plotted on the y-axis while the counting cyck as shown by the couoter outputs Q-7 is plotted on 60 the x-axis. As shown in FIG. 2, a s the counter counts upward lo the maximum count of 128, the peak switching frequency is achieved. This peak switching frequency is normalized lo be about 1.075 times [he base switching frequency. Further, on average, the switching Gequency is between 1.03 and 65 1.04 times the base switching frequency. Thus, the embodimen1 of FIG. 1 deviates the switching frequency of the

6
oscillator within a narrow range. This deviation reduces EM1 noise by spreading the energy over a wider frequency range than the bandwidth measured by the EM1 test quipment such that the noise measured by the EM1 test equipment is reduced considerably. FIG. 3 s b w s an analog frequency jinering circuit. More frequency jittering & v i a a n shown in delaik on Ibe co-pending US. application Set. No. 09AB0.774. wtiUed -OFFLINE CONVERTER w m INTEGRATED SOFT START AND FREQUENCY J m , I R" oo May 18, filed 1998, thc content of which is hereby incorporated by refere m . In HG. 3, the primaq oscillator 110 provides an willator output on lioe OSC-OUT 101. An analog low frquency d a t o r 405 is aim Primary oscillator 110 typically operates between a range of 30 to 300 kHz, while thc low freqnency oscillator 405 typically operates between a range of 5 Hz to 5 kHz.As discussed above, the switching fnqueocy of the primary oscillalor 110 is determined by the amount of current the primary oscilhtor uses to charge and discbarge capacilor 134. Tbe low frequency oscillator 405 varies this current within a narrow range to jiner the frequency of the primary oscillalor ll0. The output of low frequency oxillator 405 is provided to a MOSFET transistor 505 connected to a resistor 510 and a minor including tra&stors 495 a d 500. namistor be 508 i fonneaed lo & 123 SJ t b t exlra cumnt s added to current source 122 feeding the primary oscillator. In this manner, the frequency of the primary arcillator 110 is shifted a r o u ~ d n a m w range to reduce the EM1 noise. a FIG. 4 shows a more detailed implementation of FIG. 3. A, s b w n therein, main -illator 465 has a curnnt source 470 that is mirmred by current minor transislors 472 and 475. Main oscillator drive current 615 is provided to current of the input 4 8 of oscillator QSO. ~ current input into current source input 485 determines the frequency of the oscillation signal 415 provided by oscillator 480. In order to vary the ficquency of tbc oscillat(on signal 415, an additional current source 495 is provided within the main oscillator 465. The current source 495 is mirmnd by current soura mirror 500. ~h~ current provided by current soum 495 is as follows. F~~~~~~ sipal 400 is provided to the gate of main osciUator tralrrdor 505. As t b magnitude of bquency signal 400 incnws, docsthe vo]bge so at the sourn of main -']lator tramislor 505 due to the increasing voltage at the gate of the transistor 505 and the relatively coostant voltage drop between the gate and source of the transistor 505. As the voltage at the s o u r a of hansktor 505 increases, so docs tbe current 604 flowing through the resistor 510. The current &wing through the resistor 510 is tbe same as the current flowing through additional current source 500 which mirrors transistor 495. since t h frequency varjation signal 400 is a triangular waveform having a fixed period, as shown, the magnitude of the current input by additional currcnl source m n r 500 will io vary linearly with the magnitude of the rising and falling edges of thc frequency variation signal 400. lf the frequency variation signal 400 i s a ramp signal, the frequency will Iinearly rise to a peak and then fall to its lowest value. lo this way, the current 615 provided to current source input485 of the oscillator 480 is varied in a known fixed range that allows for an easy and accurate frequency spread of the high frequency current. Further, the variance of h e frequency is determined by tbc magnitude of tbe current provided by current source mirror 500, which is a Function of the resistance of Ihe resistor 510.

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6. The circuit of claim 2, wherein the. digital to analog a primary current source coupled to the wntrol input; and a differential switch coupled to the primary source. converter has one or more secondary current sources. 23-The circuit of claim 22 wherein the oscillator furtbcr 7. The circuit of claim 6, hrrther comprising a tramistor compd: coupled between each secondary current s o u r a and the first and secuod transistors coupled to the primary current 5 counter. source; 8. The circuit of claim 6, wherein the primary current a third tramsSor coupled lo the first transistor; and source generates a current I and each of the scwndary a fouah transistor coupled to the second t a s s o at a rnitc current sources generates a cumnt lower than I. 9. The circuit of claim 8, wherein tbc secondary current junction. 10 24. The circuit of claim 2lfurther comprising a capacitor sources generate binary weighted cunents and a comparator coupled to the junction. 10. 'lhe circuit of claim 8, wherein tbe largest secondary current sourffi generates a current which i less than about s 25. The circuit of claim 22 wherein the primary cucrent 0.1 of I. source generates a current 1 rod each of said one or more ll.A method for generating a switching frequency in a -nt sources generates a cumnt lower than I. 15 power conversion system, compriring: 26. The circuit of claim 22 wherein the primary cumnt source generates a cumnt I and each of said one or more generating a primary current; current sourfa generates a S C W c~u m n t lower than the mcling m e Or more secondan, cumnt muto eemrale * current I, brtber comprising a transistor coupled to each a secondary current which varies over time; and cOoncc'ed the countercombining the secondary current with the primary current 27. The circuit of claim 21 further comprising a transistor to be reaived at a input of an -aatorfor 20 mupled to each current source a d to the counter. a frequency which is varied over 28. The circuit of claim 21 wherein the oscillator further time comprises: l2.Tbemethod of claim 11 further comprising the step of a primary voltage souroe wuplcd to the wntrol input; and clocking a counter with tbe output of the oscillator. a differential switch mupled t the primary volbge o W. The method of claim 1 wherein the primary current 25 1 source. is generated by a current source. 14. ne melwclaim 11 wherein the primary current lhe29. The circuit of claim 21 wherein the means for varying of frequency wmprists is 1 and eacb of h e secondary currenl sources general- a supplemental current lower than I, and further comprising a and a cunent source adapted to charge and discharge the passing the supplemental current to the asciltator wntrol JO input. capacitor. 3.The circuit of claim 29 further comprising: 15. The method of claim 14 further wmprising binaryweighting tbc supplemental current. one or more comparators coupled to the capacitor; and 16. The method of claim 14 wherein the lugest supple- 35 mcam coupled to the capacitor for altematingly charging mental current is less than approximately 0.1 of I. and discharging the capacitor. 17. A method for generating a switching frequency in a 31. A power supply having a transformer coupkd to ao power conversion system, wmprling: input voltage, the transformer having a primary winding, the generaling a primary voltage; power supply comprising: cycling one or more secondary voltage sourccs to generan oscillator for generating a signal having a frequency, ate a secondary voltage which varies over time; and tbe oscillator having a control input for varying the frequency of the signal, the oscillator iocluding: combining tbe secondary voltage with the primary voltage a primary current source coupled to the control input; to be received at a conlrol input of a voltage-controlled a differential switch coupled lo the primary current oscillator for generating a switching frequency which is source; varied over time. 4s a capacitor coupled to the differential switch; and 18. Tbe method of claim 17 funhcr comprising clocking a comparator coupled to thc difFerentia1switch; a counter with the output of the oscillator. 19. The method of claim 17 wherein tbe primary voltage a digital to analog converter coupled to the wntrol input. is V and each of the sccoodary voltage s o m e s generates a the digital to analog converter having one or more supplemental voltage lower than V further comprising pass- 50 , current sources. wherein the primary current source ing the supplemental voltage to the voltage-controlled oscilgenerates a current I and each of said onc or more lator. current sources generates a current lower that I; 20. The method of claim 19, wherein the supplemmtal a counter coupkd lo the output of the osciuator and to the voltage is binary-weighted. current sources of thc digital to analog converter; and 21. A Gequency jitlering circuit for varying a power 55 a power transistor coupled lo the oscillator and to one supply switching frequency, comprisiig: terminal of the primary winding, the power transislor moduan oscillator for generating a signal having a switching lating its output in providing a regulated power supply frequency, the oscillator having a control input for output. varying the switching frequency; and 32. A power supply having a transformer coupled to an means coupled to the control input for varying the switch- 60 input voltage, the transformer having a primary winding. the power supply comprising: ing frequency, including: one or more current sources coupled to lhe control an oscillator for generating a signal having a frequency, input; and the oscillator having a control input for varying the frequency of the signal, the oscillator including: a counter coupled to the output of the oscillator and to the 65 one or more current sources. a primary current source wupkd to the control input; 22. The circuit of claim 21 wherein thc oscillator further a differential switch coupled to the primary current comprises: source;

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a capacitor coupled to the differential switch; and a comparator coupled to the differential switch a circuit for varying the frequency, the circuit mupled to thc control input, including: a capacitor. a current s o u r a adapted lo charge and discharge the capacitor; one or more comparators coupkd lo the capacitor and coupkd to tbe cumnt source for alternatiogly charging and discharging the capacitor; and

a power transistor mupled to the oscillalor and to one ~erminal the primary winding, tbc power transistor of modulating its output in providing a regulated power supply output.
5
t t + * t

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