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Case 1:07-cv-00449-JJF

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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE ON SEMICONDUCTOR CORP. and SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C., Plaintiffs, v. SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., SAMSUNG TELECOMMUNICATIONS AMERICA GENERAL, L.L.C., SAMSUNG SEMICONDUCTOR, INC., and SAMSUNG AUSTIN SEMICONDUCTOR L.L.C., Defendants. SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., SAMSUNG TELECOMMUNICATIONS AMERICA GENERAL, L.L.C., SAMSUNG SEMICONDUCTOR, INC., and SAMSUNG AUSTIN SEMICONDUCTOR L.L.C., Plaintiffs, v. ON SEMICONDUCTOR CORP. and SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Defendants. ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )

C.A. No. 07-449 (JJF) REDACTED PUBLIC VERSION

C.A. No. 06-720 (JJF)

DECLARATION OF MARTIN G. WALKER, Ph.D. IN SUPPORT OF THE REPLY BRIEF OF ON SEMICONDUCTOR CORP. AND SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC IN SUPPORT OF THEIR MOTION TO COMPEL DISCOVERY

I, Martin G. Walker, Ph.D., declare as follows: 1. I have been retained as an expert consultant by the law firm of Jones Day, counsel

of record for ON Semiconductor in the above-captioned matters. This declaration is based on

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my personal knowledge and experience as well as my investigation in this matter and reflects my expert opinions on certain issues. 2. My CV (Exhibit A) contains an overview of my thirty years of experience in the

field of Electronic Design Automation ("EDA") software systems. I received a BSEE from the Massachusetts Institute of Technology in 1973, and MSEE from Stanford University in 1976, and a PhD. in electrical engineering from Stanford University in 1979. My work experience includes direct work with EDA software, both as a developer and as a designer. 3. From 1983 to 1989, I was the founder and Chief Technical Officer at Analog

Design Tools, Inc. In my work at Analog, I was a founder and founding CEO. I was primarily responsible for writing the original business plan and raising the venture capital necessary to launch the company and recruiting the staff. Later, I was responsible for all technical aspects of product definition and development. My efforts were instrumental in growing Analog from a start-up company to a leader in the field of analog design automation. 4. From 1990 to 1994, I was a founder and Executive Vice President of Symmetry

Design System ("Symmetry"), which specialized in product design and consulting for the electronic design marketplace. In this role, I was instrumental in development of Symmetry's products. 5. In 1995, I founded a company called Frequency Technology (now Sequence

Design) ("Sequence") that develops EDA software for the design of advance system-on-a-chip integrated circuits. Sequence's products have become the de facto industry standard for parasitic extraction, circuit optimization, and RTL power analysis. As Chief Executive Office, director, and Chief Scientist at Sequence, I was involved in overseeing the development of the company's products and technologies. I also took an active role in recruiting the technical and business staff.

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6. automation. 7.

I am named as an inventor in three patents in the field of electronic design

I am familiar with the processes for designing and manufacturing semiconductor

products. I have used various EDA design tools, including those from Synopsys, Cadence, and Mentor Graphics, to both design and analyze circuits. These tools are very expensive, costing over $100,000, and time consuming to acquire and set up. Because modern semiconductor products are very complex, it is virtually impossible to design and analyze them without EDA tools. 8. Attached as Exhibit B is an excerpt from a text ("Application-Specific Integrated

Circuits" by Michael John Sebastian Smith) that describes the process of designing semiconductor products. As can be seen in Exhibit B, pg. 17, there are two broad steps in creating the design of a device: "logical design" and "physical design." The result of the logical design process is generally a netlist. A schematic is a graphical representation of a netlist. Netlists are usually maintained by EDA tools in a hierarchical database. The best way to evaluate circuits is to use EDA tools which access the native databases of the circuits at issue. The output of the physical design process is normally a GDS2 file. The physical design is also maintained by the EDA tools in a hierarchical database. 9. EDA design tools can be used to design and analyze circuitry through the use of

netlists and schematics. In particular, EDA tools analyze designs using the netlist; people sometimes prefer to use schematics, usually integrated into the EDA tools, so that the tools can be used to navigate the schematics. Since electronic devices are complex, containing millions of transistors, it is very difficult, burdensome, and time consuming to determine functionality of an electronic device by reviewing schematics separate from the EDA tools. For example, through

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the use of these schematic design tools, one would be able to navigate up or down in the hierarchy of a circuit design. The high-level view of a design can be useful to identify where certain general functionality is performed. Once an area of interest is identified, the schematic design tools then allow for traversing down the hierarchy to see the details of a particular functional block, for example, allowing for a circuit to be viewed at a lower logic level or at an even lower transistor level. This is illustrated in Exhibit B by the flow from box 2 ("logic synthesis") to box 4 ("prelayout simulation"). 10. Schematic design tools also allow for signals to be traced throughout a circuit,

including between circuit blocks, and further allow for the viewing of the attributes of a particular semiconductor device at any point of the design. More importantly, EDA design tools allow for the simulation of the circuit being designed or analyzed. This is crucial because of the complexity of modern circuits. Whereas a small block of circuitry may be analyzed manually (i.e., without EDA tools), its operation in the larger context of the entire circuit is much more complex and virtually impossible without EDA tools. 11. It is my understanding that Samsung originally produced images of certain

schematics in TIFF format. It is my further understanding that Samsung subsequently produced the same information in PDF and PS files. I am familiar with these types of files. PDF (Portable Document Format) and PS (PostScript) files are proprietary file formats from Adobe Systems and are basically the equivalent of paper print-outs of the schematics. These image files are not the manner in which analysis and design information is kept by companies such as Samsung. Image files such as PDF and PS files do not provide the design and analysis functionality of EDA tools as described in paragraphs 9 and 10, above. For example, PDF and PS files are not navigable for traversing the hierarchy of a circuit.

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12.

I am familiar with modern memory products such as those accused of infringing

in the present case. These products contain many millions of transistors. But I understand that Samsung has only produced from 71-184 pages of schematics for each particular accused product. For example, I specifically understand that Samsung produced 184 pages of images of schematics to represent one of its 512 megabyte memory products, i.e., a memory product with 512 million bits of information. Based on my experience in the semiconductor industry, it is inconceivable that the complex memory circuits with its millions of transistors can be completely represented in 184 pages of images. A schematic database, however, can fully represent the accused memory products. 13. As mentioned above, EDA tools are also used to design the physical placement of

circuitry within a semiconductor die as well as to design the physical connectivity of such circuitry. Proper physical placement is crucial to the correct operation of a final product. Because of the complexity of modern circuit, this design step cannot be performed without computerized EDA tools. Physical design information is typically represented as GDS2 (or GDSII) data. Only after the physical design is complete and known to operate as desired is GDS2 information sent to a foundry for production. GDS2 data is used by a foundry to create the actual masks used to manufacture parts. Such mask data is often maintained in a file format called "MEBES." MEBES files are distinct from GDS2 files, and contain different data including many structures necessary to realize the desired design that are not in the GDS2 data. 14. The physical design of a circuit must correspond to the schematic design (or

idealized design). In this way, schematic and GDS2 data have corresponding but not identical information. For example, where a schematic may identify the interconnectivity of a first and second transistor, there must be corresponding first and second transistors in the GDS2 data. But

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CERTIFICATE OF SERVICE I, the undersigned, hereby certify that on March 4, 2008, I electronically filed the foregoing with the Clerk of the Court using CM/ECF, which will send notification of such filing(s) to the following: Josy W. Ingersoll John W. Shaw Andrew A. Lundgren I also certify that copies were caused to be served on March 4, 2008 upon the following in the manner indicated: BY HAND AND EMAIL Josy W. Ingersoll John W. Shaw Andrew A. Lundgren YOUNG, CONAWAY, STARGATT & TAYLOR LLP The Brandywine Building 1000 West Street, 17th Flr. Wilmington, DE 19899 BY EMAIL John M. Desmarais James E. Marina KIRKLAND & ELLIS 153 East 53rd Street New York, NY 10022

/s/ Richard J. Bauer (#4828) Richard J. Bauer (#4828)

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EXHIBIT A

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EXHIBIT B

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