Free Redacted Document - District Court of Delaware - Delaware

Case 1:07-cv-00633-JJF-LPS

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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE POWER INTEGRATIONS, INC.,
Plaintiff,

C.A. No. 07-633 JJF-LPS

V. BCD SEMICONDUCTOR CORP, et al., Defendants.

REDACT ED

SECOND SUPPLEMENTAL DECLARATION OF KYLE WAGNER COMPTON IN SUPPORT OF POWER INTEGRATIONS , INC.'S OPENING SUPPLEMENTAL BRIEF IN OPPOSITION TO DEFENDANTS' MOTION TO DISMISS FOR LACK OF PERSONAL JURISDICTION FISH &RICHARDSON P.C.
William J. Marsden, Jr. (#2247) ([email protected]) Kyle Wagner Compton (#4693) ([email protected]) 919 N. Market Street, Suite 1100 P.O. Box 1114

Wilmington, DE 19801 Telephone: (302) 652-5070 Facsimile: (302) 652-0607
Frank E. Scherkenbach FISH & RICHARDSON P.C. 225 Franklin Street Boston, MA 02110-2804 Telephone: (617) 542-5070 Facsimile: (617) 542-8906 Howard G. Pollack Michael R. Headley Scott A. Penner FISH & RICHARDSON P.C. 500 Arguello Street, Suite 500 Redwood City, CA 94063 Telephone: (650) 839-5070 Facsimile: (650) 839-5071
ATTORNEYS FOR PLAINTIFF

POWER INTEGRATIONS, INC. Dated: June 6, 2008

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I, Kyle Wagner Compton, declare as follows:
1. I am an Associate with Fish & Richardson P.C., counsel for Plaintiff Power

Integrations, Inc. ("Power Integrations"). I make the following statements based on personal knowledge, except where noted.

2.

Attached as Exhibit 1 to this Declaration is a true and accurate copy of an email

from Michael Headley to Eric Puknys dated April 14, 2008. 3. Attached as Exhibit 2 to this Declaration is a true and accurate copy of a letter

from Michael Headley to Eric Puknys dated May 19, 2008. 4. Attached as Exhibit 3 to this Declaration is a true and accurate copy of an email

from Eric Puknys to Michael Headley dated May 20, 2008. 5, Attached as Exhibit 4 to this Declaration is a true and accurate copy of excerpts

from the deposition of Jonathan Wang taken on May 28, 2008
6. Attached as Exhibit 5 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0119495 - BCDS0119498.

7.

Attached as Exhibit 6 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0029016 - BCDS0029018. 8. Attached as Exhibit 7 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0076527 - BCDS0076534.

9.

Attached as Exhibit 8 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0108836 - BCDS0108839.
10. Attached as Exhibit 9 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0028747 - BCDS0028749.

2

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11.

Attached as Exhibit 10 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0028901 - BCDS0028909. 12. Attached as Exhibit 11 to this Declaration is a true and accurate copy of

Production No. BCDS0029199. 13. Attached as Exhibit 12 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0001608 - BCDS0001609.
14. Attached as Exhibit 13 to this Declaration is a true and accurate copy of BCD's

Second Revised Answer and Objection to Power Integration's First set of Interrogatories (Nos. 1-18), dated April 14, 2008.

15.

Attached as Exhibit 14 to this Declaration is a true and accurate copy of excerpts

from the deposition of Kang Chan dated April 15, 2008. 16. Attached as Exhibit 15 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0076479 - BCDS0076480. 17. Attached as Exhibit 16 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0076545 - BCDS0076549. 18. Attached as Exhibit 17 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0002221 - BCDS0002227. 19. Attached as Exhibit 18 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0076683 - BCDS0076692.
20. Attached as Exhibit 19 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0093544 - BCDS0093555

21.

Attached as Exhibit 20 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0093106 - BCDS0093130.

3

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22.

Attached as Exhibit 21 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0028857 - BCDS0028862.

23.

Attached as Exhibit 22 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0076187 - BCDS0076190. 24. Attached as Exhibit 23 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0108932 - BCDS0108938. 25. 26. Exhibit 24 to this Declaration is intentionally omitted. Attached as Exhibit 25 to this Declaration is a true and accurate copy of

Production No. BCDS0032718. 27. Attached as Exhibit 26 to this Declaration is a true and accurate copy of U.S.

Patent No. 6,980,442. 28. Attached as Exhibit 27 to this Declaration is a true and accurate copy of U.S.

Patent No. 7,099,163. 29. Attached as Exhibit 28 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0002862 - BCDS0002875. 30. Attached as Exhibit 29 to this Declaration is a true and accurate copy of

Production No. BCDS0002321.
31. Attached as Exhibit 30 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0002032 - BCDS0002033.

32.

Attached as Exhibit 31 to this Declaration is a true and accurate copy of

Production No. BCDS0000364.
33. Attached as Exhibit 32 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0047074 - BCDS0047085.

4

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34.

Attached as Exhibit 33 to this Declaration is a true and accurate copy of U.S.

Wireless Data Market QI 2008 Update, available online at http://www.chetansharma.com/US%20Wireless%20Market%2001 %202008%20Update%20%20May%202008%20-%20Chetan%20Sharma%20Consulting.pdf (last visited June 5, 2008). 35. Attached as Exhibit 34 to this Declaration is a true and accurate copy of AT&T

Wireless Responses to Subpoena, dated April 18, 2008.

36.

Attached as Exhibit 35 to this Declaration is a true and accurate copy of a May

29, 2008 e-mail from Susan Vinci to Scott Penner and a true and accurate copy of the attached document bearing production number VZW001. 37. Attached as Exhibit 36 to this Declaration is a chart I compiled reflecting state-

by-state per capita mobile wireless telephone subscriber rates for the year 2005, the most recent year for which both state population data and state mobile wireless telephone subscriber data are available, and true and correct copies of excerpts from the publications from which the
underlying population data and mobile wireless telephone subscriber data were obtained. 2005 state population data reported by the U.S. Census Bureau were obtained from the State and Metropolitan Area Data Book: 2006 (6th Ed.) at 3 (Table A-1. States --- Area and Population) available online at http://www.census.goy/prod/2006pubs/smadb/smadb-06.pdf (last visited June 3; 2008). 2005 mobile wireless telephone subscriber data reported by the Industry Analysis and Technology Division of the Federal Communication Commission's Wireline Competition Bureau were obtained from Trends in Telephone Service (2007) at 11-5 (Table 11.2 Mobile Wireless Telephone Subscribers) available online at http://hraunfoss.fcc.gov/edoespublic/attachmatch/DOC-270407A1.pdf (last visited June 3, 2008).

5

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38.

Attached as Exhibit 37 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0000835 - BCDS0000842.

39.

Attached as Exhibit 38 to this Declaration is a true and accurate copy of

BCDS0001894 - BCDS0001897. 40. Attached as Exhibit 39 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0047493 - BCDS0047509. 41. Attached as Exhibit 40 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS0191382. 42. Attached as Exhibit 41 to this Declaration is a true and accurate copy of a BCD

production document bearing production numbers BCDS029443 - BCDS029444. 43. Attached as Exhibit 42 to this Declaration is a true and accurate copy of BCD's

Answers and Objections to Power Integration's First Set of Request for Admission (Nos. 1-12), dated February 27, 2008. 44. Attached hereto as Exhibit 43 is a Summary Chart comparing BCD's

representations and the current evidence.
I declare under penalty of perjury under the laws of the United States of America that the foregoing is true and correct.

Executed this 6th day of June, 2008 at Wilmington, Delaware.

6

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Exhibit 1

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Michael Headley
From:

Michael Headley Monday, April 14,2008 4:31 PM Puknys, Erik Burns, Robert; E. Robert Yoches ([email protected]); Howard Pollack; Frank Scherkenbach

Sent:
To:

Cc:

Subject: Re: PIIBCD: motion to dismiss and scheduling

Erik, Per my voicemail of this morning, please let us know whether BCD will withdraw its motion to dismiss in view of the Court's order of this past Friday. If you will not, and in view of your voicemail indicating that Dr. Habetler will not be available for deposition before the 28th but that you would be willing to provide a brief extension to file our reply brief on the motion for preliminary injunction, we would be amenable to the following slight modification to the current schedule: 4124-25: jurisdictional depo(s) in SV 4/28: Dr. Habetler depo in ATL 511: PI suppl. brief re jdx due 518: PI reply brief on preliminary injunction due 518: BCD suppl. response re jdx due 5/19: hearing (subject to the Court's availability) We believe the supplemental discovery and briefing will allow the Court to deny BCD's motion to dismiss without any need for a hearing, but we would like to proceed with the hearing on our motion for preliminary injunction as soon as possible. Please let us know whether you are willing to propose this schedule jointly for purposes of tomorrow's call with the Court or if you have some alternate proposal--we are also available to discuss the issue further before tomorrow's hearing. Thanks. Michael

From: Michael Headley Sent: Sun 4/13/2008 8:57 P M To: Puknys, Erik; Yoches, Bob Cc: Burns, Robert; Howard Pollack Subject: RE: PI/BCD: Dr. Habetler's deposition
Erik & Bob, Let us know if we might be able to reschedule Dr. Habetler's deposition for next Monday or even Tuesday (4121 or 4122)--if you can accommodate either of those days, we ought to be able to get Howard where he needs to be and still stay on track. Thanks. Michael -----Original Message----From: Puhys, Erik [mailto:erik.~ukn~s@finne~an.com] Sent: Sunday, April 13,2008 8:12 PM To: Michael Headley Cc: Yoches, Bob; Bums, Robert; Howard Pollack Subject: RE: PIIBCD: Dr. Habetler deposition Howard,

I am very sony hear about your loss.
Michael, Let me know when you want to reschedule Habetler. Bob was going to cover it, but we'll see what dates we can work out. I'll talk to you tomorrow. Erik

From: Michael Headley [mailto:[email protected]]

Case 1:07-cv-00633-JJF-LPS
Sent: Sun 4/13/2008 3:48 PM To: Puknys, Erik Cc: Yoches, Bob; Burns, Robert; Howard Pollack Subject: Re: PIIBCD: Dr. Habetler deposition

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Erik, Howard Pollack has had a death in the family, so we may need to reschedule Dr. Habetler's deposition this week. We are looking into the various alternatives, but I wanted to let you know as soon as possible so that you can check with Dr. Habetler and your team re potential alternate dates. I will call you tomorrow once I have some further indication as to the status--let me know if there is someone else on point for Dr. Habetler's deposition that I should call instead. My apologies for the inconvenience. Sincerely, Michael Michael R. Headley Fish & Richardson P.C. 500 Arguello St., Suite 500 Redwood City, CA 94063-1526 (650) 839-5139 (direct) (650) 839-5071 (fax)

............................................................................................................................

This email message is for the sole use of the intended recipient(s) and may contain confidential and privileged information. Any unauthorized use or disclosure is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. IRS CIRCULAR 230 DISCLOSURE: Any U.S. tax advice contained in this communication (including any attachments) is not intended or written to be used, and cannot be used, for the purpose of (i) avoiding penalties under the Internal Revenue Code or (ii) promoting, marketing or recommending to another party any transaction or matter addressed herein.

This e-mail message is intended only for individual(s) to whom it is addressed and may contain information that is privileged, confidential, proprietary, or otherwise exempt from disclosure under applicable law. If you believe you have received this message in error, please advise the sender by return e-mail and delete it from your mailbox. Thank you.

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Exhibit 2

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~ireet Suite 500 Redwood City, California 94063-1526
TOO Arguello

Frederick P. Fish
1855-1930

Telephone

W.K. Richardson
1859-1951

VIA FACSIMILE & E-MAIL

650 839-5070
Facsimile

May 19,2008
Web Site www.fr.com

Erik R. Puknys Finnegan, Henderson, Farabow, Garrett & Dunner LLP (Palo Alto) Stanford Research Park 3300 Hillview Avenue Palo Alto, CA 94304-1203 Re:
ATLANTA AUSTIN BOSTON DALLAS DELAWARE MUNICH

Michael R Headley
bSo 819-5r39

Power Integrations, Inc. v. BCD Semiconductor Corp. USDC-D. Del. - Civil Action No. 07-633 JJF-LPS

Dear Erik:

I am writing to request once again that BCD withdraw its pending motion to dismiss for lack of personal jurisdiction, as originally requested in my voicemail and e-mail of April 14,2008.
In view of the additional information you must now be aware of in BCD's recent document productions, showing BCD's clear intent to serve the United States market, as well as the recent Delaware authority on personal jurisdiction (copy attached), we do not believe BCD can maintain its motion to dismiss in good faith and therefore ask once again that you withdraw it. Please let us know whether you will withdraw the motion by the close of business Thursday so that we can avoid any further expense related to jurisdictional issues, including the upcoming deposition and supplemental briefing, in addition to the upcoming case management conference in BCD's countersuit in California.

N E W YORK
SAN D l E G O S I L I C O N VALLEY TWIN CITIES WASHINGTON, DC

I look forward to your response.
Sincerely,

Michael R. Headley Enclosure

w w

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Exhibit 3

Re: PI/BCD: BCD's motion to dismiss Case 1:07-cv-00633-JJF-LPS

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Michael Headley
From: Sent: To: Cc: Puknys, Erik [[email protected]] Tuesday, May 20,2008 4:21 PM Michael Headley Burns, Robert; Yoches, Bob; Howard Pollack

Subject: RE: PIIBCD: BCD's motion to dismiss Michael, In answer to your two letters from yesterday: Yes, we believe our document production in response to the Court's order granting jurisdictional discovery is now complete; and no, we will not withdraw our motion to dismiss. If you have any questions, please let me know. Erik

From: Michael Headley [mailto:[email protected]] Sent: Monday, May 19,2008 2:29 PM To: Puknys, Erik Cc: Burns, Robert; Yoches, Bob; Howard Pollack Subject: Re: PIIBCD: BCD's motion to dismiss
Erik, Please see the attached letter and memorandum opinionlorder. Let me know if you have any trouble with the files. Sincerely, Michael Michael R. Headley Fish & Richardson P.C. 500 Arguello St., Suite 500 Redwood City, CA 94063-1526 '(650) 839-5139 (direct) (650) 839-5071 (fax) ............................................................................................................................ This email message is for the sole use of the intended recipient(s) and may contain confidential and privileged information. Any unauthorized use or disclosure is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. IRS CIRCULAR 230 DISCLOSURE: Any U.S. tax advice contained in this communication (including any attachments) is not intended or written to be used, and cannot be used, for the purpose of (i) avoiding penalties under the Internal Revenue Code or (ii) promoting, marketing or recommending to another party any transaction or matter addressed herein.

This e-mail message is intended only for individual(s) to whom it is addressed and may contain information that is privileged, confidential, proprietary, or otherwise exempt from disclosure under applicable law. If you believe you have received this message in error, please advise the sender by return e-mail and delete it from your mailbox.

Re: PIJBCD: BCD's motion to dismiss Case 1:07-cv-00633-JJF-LPS
Thank you.

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Intentionally Omitted

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(12)

United States Patent
Lv et al.

(10) (45)

Patent NO.: US 6,980,442 B2 Date of Patent: Dec. 27,2005
References Cited
U.S. PATENT DOCUMENTS

(54) 384X-BASED BURST MODE PWM CONTROLLER (75) Inventors: Shu Zhuang Lv, Shanghai (CN); Xu Guang Zhang, Shanghai (CN); Xin Wu, Shanghai (CN) (73) Assignee: BCD Semiconductor Manufacturing Limited, Grand Cayman (KY)

(56)
4,740,879 5,313,381 5,995,384 6,208,538 6,307,356 6,822,884 6,856,519 6,879,501

A * 411988 Peruth ........................ 3631131 A * 511994 Balakrishnan .............. 3631147 A * 1111999 Majid et al. ............. 363121.18 B1 * 312001 Halamik et al. .............. 363141 B l * 1012001 Dwelley ..................... 3231282 B l * 1112004 Rosenthal et al. ............ 363159 B2 * 212005 Lin et al. ...................... 363116 B2 * 412005 Mori ....................... 363156.03

* cited by examiner
( * ) Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. Primary Examiner-Adolf Berhane (74) Attorney, Agent, or Firm-Birch, Birch, LLP (57) Stewart, Kolasch &

(21) Appl. No.: 111036,041 (22) Filed: (65)

ABSTRACT

Jan. 18, 2005

Prior Publication Data US 200510185427 A1 Aug. 25,2005

(30) Foreign Application Priority Data Feb. 19, 2004 (CN) ........................ 2004200023842 (51) Int. CL7 ........................................ H02M 31335 (52) U.S. C1. ................................... 363121.1; 363121.18 (58) Field of Search .......................... 363121.04, 21.05, 363121.1,21.12,21.13,21.18,26,41,97, 3631131

A 384X-based burst mode PWM controller includes an oscillator to generate a pulse signal of a constant frequency, an output circuit to generate an output signal based on the pulse signal, an error amplifier to generate an amplified error signal, a logic control current source connecting to a current sense input of a comparator, the comparator which compares the voltage of the current sense input with the voltage of the error signal to generate a comparison signal, a PWM latch to generate a pulse control signal corresponding to the pulse signal and based on the comparison signal. The pulse control signal controls the output circuit and the logic control current source in opposite conditions of turning on and off. The controller can replace 384X directly and save energy.

5 Claims, 5 Drawing Sheets

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-7

automatic circuit

-

\

I

voltage reference circuit

-

Logic control circuit

C

\
Error amplifier

=- osci 1 lator"

h
Comparator
-

C

PWM Latch

118-t Logic control current source

Fig. 1

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U.S. Patent

Dec. 27,2005

Sheet 2 of 5

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PWM Mode

Time Time

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Fig.5 PRIOR ART

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384X-BASED BURST MODE PWM CONTROLLER

2

and a capacitor (shown by 409 and 410 in FIG. 4) to alter the constant frequency and the maximum duty cycle of the pulse signal. The output circuit 110 has a power supply input end FIELD OF THE INVENTION 7, a ground end 5 and a signal output end 6. The power s supply input end 7 receives an output of the external power The present invention relates to a pulse width modulation supply, and generates an output signal based on the logic control signal generated by the logic control circuit 106 and (PWM) technique and particularly to a 384X-based burst mode PWM controller. the pulse signal generated by the oscillator 108 to provide the external circuit through the signal output end 6. BACKGROUND OF THE INVENTION 10 The error amplifier 112 has a compensated output end 1 and a voltage feedback input end 2. When in use, the ports 384X series PWM controller is an industrial standard IC of 1 and 2 are bridged by an external resistor and a capacitor for power supply control, and it is widely used in AC-to-DC in a parallel manner (shown by 405 and 406 in FIG. 4) to switching power supply for electronic products such as compensate gain and frequency. The error amplifier 112 computes, TVs, DVDs. IS generates an amplified error signal based on the reference The household appliances and ofice equipments used by voltage of the voltage reference circuit 104 and the voltage people in life and work every day generally employ switchfeedback signal output by the external circuit received by the ing power supplies. The light load and standby mode funcvoltage feedback input end 2. A comparator 114 provides a tions are a big issue and have received a lot of attention from current sense input 3 to compare a current sense signal government institutions. In U.S.A. there is a government 20 voltage fed to the current sense input 3 by the external circuit decree in Jul. 2001 ordering electric equipment procured by and the voltage of the amplified error signal to generate a government institutions ought to have standby power loss comparison signal which is provided to a PWM latch 116. less than 1W. The environmental protection organizations in The PWM latch 116 corresponds to the comparison signal other countries also set up similar plans and standards. For and the pulse signal transferred from the oscillator 108 to instance, the "Energy-star" of U.S.A and "Blue Angel" of 2s generate a pulse control signal. The potential of the pulse Germany are standards adopted by a growing number of control signal determines the output circuit 110 on and off. areas. During operation, when the system starts in a normal Chinese government also takes a serious look on the condition and carries a load, the signal voltage at the current energy conservation issue. Energy saving procurement is a sense input 3 of the comparator 114 rises gradually from policy actively implemented. And China Energy Saving 30 zero. The input signal voltage at another end of comparator 114 is provided by the error amplifier 112 according to the Product Authentication Center also embarks a series of research projects. The first one is the energy conservation voltage feedback signal output by the external circuit. The authentication project for standby power consumption of error signal voltage of the error amplifier 112 is greater than the voltage of current sense signal. The comparator 114 color TV. It plans to target two to three products every year for energy conservation authentication, including video 3 s generates a comparison signal based on the comparison products such as DVD, VCD and business machines such as result and provides to the PWM latch 116. The PWM latch 116 may be a RS trigger with a control end to receive the printer, facsimile machine, computer and the like. Hence how to reduce the standby power loss of the product has pulse signal of the oscillator 108 and another control end to receive the comparison signal of the comparator 114. When become an important research subject for most power supply manufacturers. The research of chip manufacturing for 40 the pulse of the oscillator 108 is activated, the PWM latch 116 generates a pulse control signal based on the comparison reducing power loss under light loads and standby mode has signal to turn on the output circuit 110. Thereby the output some progresses. A few known semiconductor manufacturing companies have introduced green low power consumpcircuit 110 outputs the pulse signal from the oscillator 108 tion power supply control chips, such as NCP120X series of to the external circuit. When the voltage of the current sense Onsemi, FAN7601 of Fairchild, ICE2ASO1 of Infineon, 4s signal rises and is greater than the voltage of the error signal, TEA1533 of Philips, SG684X series of System General, and the comparator 114 reverses, the pulse control signal conthe like. dition generated by the PWM latch 116 also changes, such Most power supply users now use 384X controllers. They as from a high potential to a low potential, to turn off the urgently need a new chip that can save energy to replace the output circuit 110. The current sense signal becomes zero. 384X chip. However, the chips mentioned above do not so As the voltage feedback signal output by the external circuit equip such a capability. still exists, the error signal of the error amplifier 112 also FIG. 5 illustrates the block diagram of a conventional exists. Meanwhile, the voltage of the current sense signal is 384X controller 500. The automatic circuit 102 has a power smaller than the voltage of the error signal. The comparator supply input 7 to receive the input of an external power 114 is reversed again. When the pulse of the oscillator 108 supply and a ground end 5 to provide electric power to a ss reaches the PWM latch 116, the output circuit 110 turns on voltage reference circuit 104. The voltage reference circuit again to complete an on-and-off cycle. Anumber of on-and104 provides an accurate reference voltage for a logic off cycles are repeated. As the time of turning off the output control circuit 106 and an error amplifier 112, and outputs circuit 110 is very short, the waveform of the output signal the reference voltage to an external circuit through a referforms a continuous pulse wave. Such an operation fashion is ence voltage output end 8. The logic control circuit 106 60 called the PWM mode. receives the reference voltage to generate a logic control When the system is in a light load or a standby condition, signal. the error signal generated by the error amplifier 112 is smaller when the load is carried, then the time of the voltage There is an oscillator 4 with a control input end 4 which receives a control signal from the external circuit. A pulse of the current senseing signal risen and greater than the signal of a constant frequency is generated based on the 65 voltage of the error signal is shortened, PWM duty cycle is control signal. The pulse signal is provided to an output also shortened. The output waveform is still a continuous pulse waveform same as in the PWM mode at a smaller duty circuit 110. The control input end 4 is connected to a resistor

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cycle with the frequency same as the oscillator 108. Energy consumption is no big different from the normal operation condition. The present invention aims to provide an energysaving controller on this basis.

4

FIG. 2 is a fragmentary circuit diagram of an embodiment of the present invention to implement burst mode mode. FIG. 3 is a chart showing output waveform comparison of the PWM mode and the burst mode mode. s FIG. 4 is an application circuit diagram of the burst mode PWM controller of the invention. SUMMARY OF THE INVENTION FIG. 5 is an internal block diagram of a conventional 384X controller. The present invention aims to provide a burst mode PWM controller based on the backgro;nd mentioned above. DETAILED DESCRIPTION OF THE The present invention is a 384X based burst mode PWM PREFERRED EMBODIMENTS controller. It includes an oscillator to generate a pulse signal of a constant frequency, an output circuit to generate an Please refer to FIG. 1 for the internal block diagram of an output signal based on the pulse signal and send the output embodiment of the burst mode PWM controller of the signal to an external circuit, an error amplifier to receive a present invention. Compare with the conventional 384X voltage feedback signal from the external circuit and gencontroller, the controller of the invention adds a logic control erate an amplified error signal, a comparator which has a current source 118. The input and output ports have no current sense inuut on one end to receive the current sense changes. In an embodiment of the invention, when the logic signal voltage of the external circuit and another end to control current source 118 is activated, it generates a voltage receive the amplified error signal and compare the current through external resistors (shown by Rf and Rs in FIGS. 2 sense signal voltage with the amplified error signal voltage and 4) to provide the comparator 114. The comparator 114 to generate a comparison signal, and a PWM latch to compares the voltage of the current sense input 3 and the respond to the pulse signal and generate a pulse control error signal voltage of the error amplifier 112 to generate a signal based on the comparison signal. The pulse control comparison signal. The PWM latch 116 generates a pulse signal controls the output circuit on and off. When the control signal at a potential to turn on and off the output voltage of the current sense signal is smaller than the voltage circuit 110 and the logic control current source 118. The of the error signal, the output circuit turns on. When the conditions of turning on and off the output circuit 110 are voltage of the current sense signal is greater than the voltage opposite to the logic control current source 118. of the error signal, the output circuit turns off. The burst Referring to FIG. 2, when the embodiment is in operation mode PWM controller further includes a logic control and the system carries a normal load, if the error signal current source which has an output end connecting to the voltage of the error amplifier 112 is greater than the voltage current sense input of the comparator. The pulse control of the current sense signal, the PWM latch 116 generates a signal generated by the PWM latch controls the logic control pulse control signal of a high potential to turn on the output current source and the output circuit on and off in opposite circuit 110 but turn off the logic control current source 118, conditions. thereby the output circuit 110 sends the pulse signal from the When in use for switching AC-DC, on the one hand, the oscillator 108 to the external circuit. When the voltage of the u output voltage is feedback to check alteration of the load, current sense signal is greater than the error signal voltage, and is feedback to the error amplifier of the burst mode the pulse control signal generated by the PWM latch 116 PWM controller through a photoelectric coupler. On the changes from the high potential to a low potential to turn off other hand, when the controller outputs a pulse to set ON a the output circuit 110 and turn on the logic control current power tube, the peak current passing through the primary source 118. But in the load carrying condition, the voltage coil of the switching power supply transformer is detected VS is higher, the logic control current source 118 cannot through a sense resistor. When the controller turns off the flow to the external RF and RS network, thus is not effective. output to set off the power tube, the internal current of the The controller 100 is in a normal PWM operation condition, controller generates a corresponding voltage that is sent to and the waveform of the output signal is a continuous pulse the comparator to change the output condition thereof. waveform as shown in FIG. 3. Therefore the light load or the standby burst mode may be In the light load or the standby condition, when the achieved to save energy. voltage of the current sense signal rises and is greater than The burst mode PWM controller of the invention is a the error signal voltage, the pulse control signal of the PWM green power supply controller to replace the standard 384X latch 116 changes to a low potential to open the logic control series PWM controllers. Users do not have to change the current source 118 and close the outuut circuit 110. Meanconfiguration of the peripheral elements of the original while, the system voltage VS is very low in the light load or application system to achieve the benefit of low energy the standby condition, the logic control current source 118 consumption in the light load or the standby condition. It generates current flowing through RF and RS to generate a conforms to the international green power supply standards ss voltage value which is applied to the current sense input 3 of the comparator 114 through a RC filter network 120 such as Blue angel and Energy-start standards. The controlconsisting of RO and CO (it is to be noted that the RC filter ler thus constructed can directly substitute 384X controller network is not mandatory). Thus the signal voltage of the and achieve energy saving. current sense input 3 does not drop to zero because of The foregoing, as well as additional objects, features, and turning off the output circuit 110. On the other hand, the advantages of the invention will be more readily apparent 60 error signal voltage generated by the error amplifier 112 is from the following detailed description, which proceeds smaller when carrying the load, but the signal voltage at the with reference to the accompanying drawings. current sense input is still greater than the error signal BRIEF DESCRIPTION OF THE DRAWINGS
6s

FIG. 1 is an internal block diagram of an embodiment of the burst mode PWM controller of the present invention.

voltage, the comparator 114 does not reverse, and the control signal of the PWM latch 116 maintains at the low potential, the output circuit 110 and the logic control current source 118 maintains respectively in an on-and-off condition, the output signal becomes a zero signal. As time moves

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on, the external output voltage decreases, the error signal an output circuit for generating an output signal based on voltage generated by the error amplifier 112 gradually the pulse signal and sending the output signal to an increases; after a period of time, the error signal voltage is external circuit; greater than the signal voltage of the current sense input, and an error amplifier for receiving a voltage feedback signal the comparator 114 is reversed, the pulse control signal s from the external circuit and generating an amplified changes from the low potential to the high potential, and the error signal; output circuit 110 turns on, while the logic control current a having a current sense input on one end to source 118 turns off, and the controller 100 outputs again a receive a voltage of a current sense signal from the pulse waveform. The cycle set forth above is repeated, and external circuit and another end to receive the amplified the output waveform looks like jumping over many switch10 error signal, and comparing the voltage of the current ing cycles and becomes a serial of pulses at a constant sense signal with the voltage of the amplified error frequency as shown in FIG. 3. This can reduce switchinging signal to generate a comparison signal; and loss. And such an operation is called the burst mode mode. a PWM latch for responding the pulse and generIt is known to those skilled in the art that the control signal ating a pulse control signal based on the comparison may be low potential or high potential. In the aforesaid the Output circuit On and embodiment, when the error signal voltage is greater than wherein the output circuit turns on when the voltage of the the signal voltage of the current sense input 3, the pulse current sense signal is smaller than the voltage of the control signal may be low potential, and the pulse control error signal; the output circuit turns off when the signal turns on the output circuit 110 and turns off the logic voltage of the current sense signal is greater than the control current source 118. This should be within the scope 20 voltage of the error signal; of the invention. The controller 100 may also include an overheat protecwherein the burst mode PWM controller further including tion circuit connecting to the oscillator 108. It may be a a logic control current source which has an output end thermostat. When the internal temperature exceeds connecting to the current sense input of the comparator; 150.degree.C., the overheat protection circuit stops the wherein the pulse control signal generated by the PWM operation of the oscillator 108. When the temperature drops 25 latch controls the logic control current source and the to 130.degree.C., the overheat protection circuit resumes the output circuit in opposite conditions of turning on and operation of the oscillator 108. off. Referring and 5, the and Output ends 2, The burst mode PWM controller of claim 1 further the PWM controller 100 (marked by numerals 1-8) are same including: as the conventional 384X controller. In the typical AC-DC 30 an automatic circuit which has a power supply input end applications, the controller 100 of the invention can replace and a ground end to receive input of an external power the conventional controller without altering the configurasupply; tion of the peripheral components and achieve energy saving a voltage reference circuit which has a reference voltage effect. output end, the voltage reference circuit receiving Refer to FIG. 4 for a typical application circuit 400 of the Power supply from the automatic circuit to generate a burst mode PWM controller 100 of the invention. The pins 35 reference voltage which is the output to the external serial numbers 1-8 correspond to input and output end circuit through the reference voltage output end; and number 1-8. The actuation resistor Rc aims to activate the a logic control current circuit to receive the reference circuit. The output pulse passes through a noise suppression resistor 411 to actuate a switching tube Q1. Output voltage voltage of the voltage reference circuit to generate a Vout is feedback to the error amplifier 112 through a resistor 40 logic control signal which is sent to the output circuit 404, a photoelectric coupler 403 and the voltage feedback to control the output signal; input end 2 of the controller 100. A capacitor 405 and a wherein the voltage reference circuit further sends the resistor 406 are gain and frequency compensation elements. reference voltage to the error amplifier, the oscillator The circuit set forth above forms an output voltage feedback having a control input end to receive a control signal control. In addition, the resistor Rs takes peak current sense 45 from the external circuit to generate the pulse signal, input of the primary coil of a transformer TI, through a filter the output circuit having a power supply input end to network (resistor Rf and capacitor 407) and the current sense receive input from an external power supply, a ground input 3, feedback to the comparator 114 of the controller 100 end and a signal output end to output an output signal to complete current feedback. to the external circuit, the error amplifier having a The burst mode mode of the system wherein the controller 100 resided can be implemented through the voltage feedfeedback receive a feedback signal from the external circuit and a compensation back and the current feedback previously discussed. Moreoutput connecting to the external circuit to compensate over, the output power setting point in the burst mode mode gain and frequency for the error amplifier. is adjustable. By altering the filter network (resistor Rf and 3. The burst mode PWM controller of claim 1, further capacitor 407) and the output resistor and capacitor network (404 and Clo), the system may be transferred to the power 55 including a RC filter circuit which includes a resistor and a capacitor, the resistor bridging the output of the logic control level of the burst mode mode. current source and the current sense input of the comparator, Furthermore, the invention employs a special circuit structure so that when operating in a power supply system, the capacitor bridging the current sense input of the comthe internal loss of the controller and thermal loss of the parator and the ground. actuation resistor and dummy load are significantly lower 60 4. The burst mode PWM controller of claim 1, wherein than the standard 384X controllers now on the market. the PWM controller is a RS trigger. What is claimed is: 5. The burst mode PWM controller of claim 1, further 1. A 384X-based burst mode PWM controller, comprisincluding a temperature protection device to protect the ing: oscillator from overheating. an oscillator for generating a pulse signal of a constant 65 frequency; * * * * *

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(12)

United States Patent
Ying

(10) (45)

patent NO.: Date of Patent:
B1 * 712004 B1 * 112005 B1 * 312005 B1 * 612005 B1 * 612005 B1 * 1212005

US 7,099,163 B1
Aug. 29,2006

(54) PWM CONTROLLER WITH CONSTANT OUTPUT POWER LIMIT FOR A POWER SUPPLY (75) Inventor: Zheng Ying, Shanghai (CN) (73) Assignee: BCD Semiconductor Manufacturing Limited, Grand Cayman (KY)
\ ,

6,768,655 6,839,247 6,865,093 6.903.945 6,906,934 6,972,969

Yang et al. .............. 363121.01 Yang et al. .............. 363121.11 Disney ...................... 363121.1 Kitano .................... 363121.01 Yang et al. ................... 363149 Shteynberg et al. ..... 363121.12

* cited by examiner
Primary Examiner-Adolf Berhane (74) Attorney, Agent, or Firm-Birch, Birch, LLP Stewart, Kolasch &

( * ) Notice:

Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 111271,901 (22) Filed:
Nov. 14, 2005

(57)

ABSTRACT

(51) Int. C1. H02M 3/335 (2006.01) (52) U.S. C1. ...................................... 363121.11; 363149 (58) Field of Classification Search .................. 363120, 363121.01, 21.1, 21.11, 21.18, 41, 49 See application file for complete search history. (56)
References Cited U.S. PATENT DOCUMENTS
5,828,558 A * 1011998 Korcharz et al. ............. 363120 6,577,509 B1 * 612003 Deboy et al. ................. 363120 6,661,679 B1 * 1212003 Yang et al. ................... 363141

A PWM controller has a line voltage input that allows using a start-up resistor for both start-up and power-limit compensations so that it can save the power consumption, ease the PCB layout, and shrink the power supply size. In the integrated circuit, a current switch used for both start-up and line voltage sensing is composed of a diode and a switch transistor. A current multiplier is used to improve the precise by canceling the impact of the integrated resistor's absolute value, which is composed of a transistor loop, a constant current and a reference current. Thus, by properly selecting the value of the start-up resistor, an identical output power limit for low line and high line voltage input can be achieved. 2 Claims, 5 Drawing Sheets

Vin

, / 300
Vout

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PWM CONTROLLER WITH CONSTANT OUTPUT POWER LIMIT FOR A POWER SUPPLY FIELD OF THE INVENTION The present invention relates to a power supply. More particularly, the present invention relates to the pulse width n~odulation(PWM) of a switching mode Power COnverter.

2
line voltage. Thus the output power (P) of a PWM power supply can be calculated as follows:

where is the energy transfer ratio from primary to secondary.Assuming the load is constant, as Vin varies from low to high, the output voltage (Vout) will be kept constant BACKGROUND OF THE INVENTION by automatically adjusting the toN through the feedback control loop of the power supply, and toN can be calculated (4) and the (5). The PWM is a traditional technology used in the switch- ,, from the ing mode power converter to control the output power and achieve the regulation. Most of the equipments, such as NX(~-D) Vin= - V O U ~ I) x mobile phone, TV game, computer and so on are using PWM power converters to supply power and charge battery. [ON Various protection functions such as over-voltage and over- 20 D = T current protection are built in the power supply to protect the power supply and the load from permanent damage. The Where N is the tUm-011 ratio, but the maximum ON is function of output power limit is generally used for the restricted and can be expressed as the equation (6) when the over-load and short circuit protection. 25 voltage in the VS pin is higher than a power limit voltage Referring to FIG. 1, it shows a conventional application V,,,,,, such as 1V in the PWM-control IC UC384X. circuit of the PWM power supply. A PWM controller 10 controls the power output and achieves the regulation. The operation of PWM-control starts on the charging of a Vl,,,, x Lp to, = start-up capacitor 18 via a serial start-up resistor 12 when the 30 Vin x Rs power is turned on until the supply voltage VCC reaches the threshold voltage, and then the PWM controller 10 starts to Rs is the resistance of a current sense resistor 11 which is output a PWM signal and drive the entire Power supply. added between the source ofthe power MOSFET 17 and the After the start-up, the VCC is provided from 35 ground for current sensing, Furthemore, the maximum the auxiliary bias winding of the transf~rmer through a 20 output power (P,,,) is also affected by the PWM controlrectifier 19. A resistor 11 that is connected serially with the ler's 10 response time tD, From the moment that the voltage power metal-oxide semiconductor field-effect transistor in the VS pin is higher than the power limit voltage to the moment that the PWM controller's 10 OUT pin is actually (MOSFET) 17 determines the maximum output power of the . , power supply. The method is to connect the voltage (VS) of 40 off, there is a delay time t ~ Within this delay time t ~the resistor 11 to the current-sense input ofthe PWM controller power MOSFET 17 is still on, and it will continue delivering power. Therefore, the actual tum-on time of the PWM signal 10, If the voltage VS is greater than the maximum currentto and the maximum Output sense voltage such as lV, the PWM controller 10 will disable (P,,,) becomes as follows: the output of its OUT pin and restrict the maximum power 45 output of the power supply. The energy stored in an inductor is given by
10
A

>

50

1 E=-XL,XI;=PXT 2

(1)

55

Where IP and LP are the peak current and the primary inductance of the transformer 20 respectively, and T is the PWM switching period. The peak current Ip can be expressed as follows:
60

vin I, = -x to, LP

(2)

65

Where toNis the turn-on time of the PWM signal in which the power MOSFET 17 is switched on, and V,, is the input

Although the tD time is short, generally within the range of 150-200 ns, the higher the operating frequency is, the more impact is caused by tD because the switching period T is short and tD becomes relatively more important. Normally, tD is a constant time determined by the controller's speed. Thus, the maximum output power P , from the equation (7) will vary as the input line voltage V,, varies. When the safety regulations are taken into consideration, the range of the input line voltage Vin is from 90Vac to 264Vac, wherein the output power limit (P,,,) of the power supply in high line voltage (Hight) is many times higher than the output power limit (P,,,) in low line voltage (Low). If power limit voltage V,,,,, is constant, the max output power P , will vary with the line voltage, as shown in FIG. 2. That's why line compensation is needed. And, a high voltage across the resistor 13 causes inconvenience for the component selection and printed circuit board (PCB) layout.

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SUMMARY OF THE INVENTION

4

The drain of the switch transistor 112 and the anode of the diode 111 are connected to form an input of the current The present invention provides a PWM controller having switch unit 110. A start-up resistor 210 is connected between a line voltage input that allows using one resistor for chip the input voltage Vin and the input of the current switch unit start-up and line voltage sensing so that it can save the Power 5 110. The cathode of the diode 111 is connected to the power ease the PCB layout, and the Power supply voltage VCC. The gate of the switch transistor 112 is size. The PWM comprises a current controlled by the under-voltage lockout unit 190. The source switch, a current multiplier, a reference current and a current ofthe switch transistor 112 is connected to the input terminal adder to start up the power and 'Ompensate the of the current multiplier 120. The output of the current output power limit. l o multiplier 120 is connected to the negative input terminal of A start-up resistor is connected from the input voltage to the current adder 130. The reference current 140 is conthe current switch unit to provide an input current for the nected to the positive input terminal of the current adder PWM controller, wherein the variation of the input current 130. The output current of the current adder 130 is transis directly proportional to the change of the input voltage formed to a voltage signal by a resistor 131. Isolated by the Vin. The current switch includes a diode and a switch 1s buffer 150, the power limit voltage V,,,,, is connected to the transistor. During the start-up, the switch transistor is closed positive input terminal of the first comparator 181. The by an under-voltage lockout (WLO). The start-up diode negative input terminal of the first comparator 181 and the transparently drives the input current to charge up a start-up second comparator 182 are connected to the source of a capacitor. When the supply voltage VCC reaches the power MOSFET 220. The current I, flowing through a WLO's the PWM starts to 20 resistor 221 produces a sense voltage VS in the resistor 221. operate, the switch transistor is turn-on by the W L O and Once the power is turned On, the input current the start-up diode is reverse biased. The input current flows the current switch unit 11° through the start-up into the current multiplier to generate an offset current. The resistor 210. Because the switch transistor 112 is closed by current adder subtracts the offset current from the reference current, ~ h r a ~ ~ ~a power limit voltage is pro- 25 the under-voltage lockout unit 190, all input current flows resistor, h the and starts charge up the start-up duced. Because the offset current is a function of the input capacitor 230. When the voltage in the start-up capacitor 230 line voltage, the variation of the power limit voltage is reaches the threshold voltage of the under-voltage lockout inversely proportional to the deviation of the input voltage. unit l 9 O > the PWM loostarts 'perate. The Besides, by selecting a proper start-up resistor, an identical output power limit can be achieved for low line and high line 3o switch transistor 112 is opened by the under-voltage lockout unit 190, the diode 111 is reverse biased, and then all input voltage input. current I flows into the current multiplier 120. After that, , A resistor is needed to transform the current to the the supply voltage VCC will be provided from the auxiliary voltage, however it is difficult to design a precise resistor inside the integrated circuit. A current multiplier is used to winding a transformer 300. The current vary 35 proportionately the input line cancel out the impact of the resistor's absolute value. BRIEF DESCRIPTION OF THE DRAWINGS
Vin - V,, - Vh Vin
z Rstarrup Rsranup

FIG. 1 is a conventional application circuit of the PWM power supply. FIG. 2-shows the time diagram of the conventional application circuit if V,,,,, is constant, the max output power P , will vary with line voltage. FIG. 3 is the block diagram of the PWM controller of a u preferred embodiment of the present invention and connected circuits therewith. FIG. 4 is the detailed circuit inside the integrated circuit of the present invention. FIG. 5 shows the time diagram of the present invention if the variation of V,,,,, is inversely proportion to the deviation of the input line voltage Vin, the output power limit will be identical. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed descriptions for content and technology of the present invention associated with figures are as follows. Please refer to FIG. 3. It is the block diagram of the PWM controller of a preferred embodiment of the present invention and connected circuits therewith. The PWM controller 100 comprises a current switchunit 110 composed of a diode 111, a switch transistor 112, a current multiplier 120, a current adder 130, a reference current 140, a buffer 150, an oscillator 160, a flip-flop 170, a first comparator 181, a second comparator 182, a NAND gate 183 and an undervoltage lockout unit 190.

/IN

=

(8)

40

In equation (a), Rsta,tup is the resistance of the start-up resistor 210; V,, is the gate-to-source voltage of the transistor 121; and V, is the drain-to-source voltage of the , switch transistor 112. The input current I is transferred to the offset current 10s by the current multiplier 120. 10s can be estimated as
IOS=KXI,

(9)

50

is a decided the design. The current adder 130 subtract the 10s from the Iref (reference current), the result Isum can be expressed as
Isum=Iref-Ios=Iref-KxIIN
(10)

55

The V,,,,, equals the voltage across the resistor 131 and is isolated by the buffer 150 which determines the maximum output power,

60

vin V,,,,, = RI31 x Isurn = RI31 x /ref - K x RI31 x Rsranup

(11)

65

Where V,,,,, is the maximum current-sense voltage that VS can be achieved. R,,, is the resistance of resistor 131. The resistor 221, which is connected to the source of the power MOSFET 220, plays the role of I-to-V transforma-

Case 1:07-cv-00633-JJF-LPS

Document 106-2

Filed 06/13/2008

Page 73 of 127

tion. As the current I, increases, which flows through the power MOSFET 220, the voltage VS in the resistor 221 will also rise up. The first comparator 181 will compare the voltage VS and the voltage V, , When the VS is greater then V,, the first , . , comparator 181 will output a logic low signal to the input of a NAND gate 183. Thus, the NAND gate 183 will output a logic high signal to reset a flip-flop 170 to turn off the power MOSFET 220. Therefore, the output power limit is achieved. It is to be understood that if the value of the resistor 131 is a constant, from equation (111, the variation of the maximum current-sense voltage Vmax is inversely proportion to the deviation of the input voltage Vin. By properly selection, the start-up resistor 210 can achieve an identical output power limit for the low line voltage and high line voltage such as 90Vac and 264Vac, as shown in FIG. 5. However, it is difficult to design a precise resistor 131 inside the integrated circuit. Most integrated resistors have tolerance of 220 to 30%. Our design depends on the resistors' matching to obtain the precision and performance, as shown in FIG. 4. To set Iref in equation (11) to,

Then from equations (14)-(17) and rearranging, 10s can be calculated as:

5
'OS

~ . / I N x ~ . -

v,,

= 'I3 =

'

Icon

R31

= K . IIN

Vref 1 K = a . b . C . -. Icon R~~~
lo

Irej = R141

Where Vref is a reference voltage, R141 is the resistance of resistor 131. We assume that the resistor 131 and the resistor 141 are well matched, then the first item in equation (11) is a constant. From the base-emitter loop and Kirchoff s voltage low,
Vbe,-Vbe,=Vbe,-Vbe,
(13)

We assume that the transistors are well matched from equation (13),

11 + 4
4

4 +1 3 4

(14)

Where a, b, c are correspond current ratios. Equation (19) shows that if the resistor 131 and the resistor 141 are well matched, the coefficient of the second item in equation (11) ,, is also a constant. Although the invention has been explained in relation to its preferred embodiment, it is not used to restrain the invention. It is to be understood that many other possible modifications and variations can be made bv those skilled in 20 the art without departing from the spirit and scope of the invention as hereinafter claimed. What is claimed is: 1.A PWM controller for controlling an output power limit of a power supply, comprising: a current switch unit, having a first terminal connected to 25 a line input voltage of the power supply via a start-up resistor, a second terminal coupled to a power supply voltage, a third terminal connected to an under-voltage lockout unit. and a four terminal: a current multiplier, having a first terminal coupled to the 30 four terminal of the current switch unit, and a second terminal; an adder, having a negative input terminal coupled to the second terminal of the current multiplier, a positive 35 input terminal coupled to a reference current, and an output terminal; a resistor, having a first terminal coupled between the third terminal of the adder, and a second terminal coupled to a ground voltage; a buffer, having a between the 40 output terminal of the adder and the first terminal of the resistor, and an output terminal; a first comparator, having a positive input terminal coupled to the output terminal of the buffer, a negative
A

>

45

Where I, is the collector current of transistor Tn (n=l-4). From FIG. 4 and Kirchoff s current low,
(15) (16)

, ,
<"

, Where Icon is a constant current. If the current gain 0 of the transistor T3 is large, the T3's base current can be neglected, thus
(17)

55

input terminal, and an output terminal; a second comparator, having a positive input terminal coupled to the supply voltage, a negative terminal coupled to the negative terminal of the first comparator, and an output terminal; a NAND gate, having two input terminals coupled to the output terminals of the first and second comparators, and an output terminal; and a fliv flov, couvled to the outvut termin