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A` Case 1:04-cv-01371-JJF 1 Document 173-9 Filed O1/23/2006 Page 1 014 .

Case 1:04-cv-01371-JJF Document 173-9 Filed O1/23/2006 Page 2 of 4
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-25, N0. 11, NOVEMBER 1978 1325
Tradeoff Between Threshold Voltage and Breakdown in High- $¤·"=· V Gm i °*°‘*·
. Voltage Double-Dirrusea Mos rmmmm
mr
M. D. rocna, J. D. PLUMMER, AND J. D. MEINDL N Ch _nn_ I nM__n Pi
Abstract-The design of junction isolated DMOS transistors suitable W Comm www
for monolithic integration has been studied. The purpose of this cor- _
respondence is to describe one of the key tradeoffs when designing P
these devices for high breakdown voltages (200 V for our example). lt
is a tradeoff primarily between threshold voltage and the punchthrough _ _
vciingc of thc chnnnci dimicicn_ hcwcvcn thc cvnicnchc hmkccwn Fig. 1. Cross·sect1onal structure of a high-voltage DMOS transistor.
voltage, on-resistance, and source-to-substrate punchthrough voltage are
’}’° f*“°°*°d· M °“ °"f““P‘$· “‘° d°‘i8“ °f ‘ d°"i°° f°’ 2°°'V °P°‘*' device is dominated by the resistance of the drift region be-
¤°“"d°‘°‘"’°d· The d*’°““‘°“ i‘•h°w°“’·$°“°“l md °“‘ b° ’pPu°d tween the channel diffusion and the drain contact for high-
*° °'h°' DMOS d°'i$““ “ “'°u· voltage designs. This resistance was, furthermore, shown to be
inversely proportional to the impurity concentration in the
I_ Inrggpucrrou epitaxial layer Nd. In this correspondence we show that the
High-voltage double-diffused MOS (DMOS) transistors have ggfxitgiglgg ¥i?;;1;?;m°;gh vfztiigi liiflsgmaffgcigd bf; Nil
been fabricated in monolithic integrated circuits operating at This unchthréugh vOi:;’c Zgiaisca fgmtion si? tgc cvgtagggi
voltages up to 200 V, for a new Ult1‘¤5¤11i¤ im¤8i¤8 $Y$t°m UL la gr pjmpuyjt ggncentraiion thereb rovidin R linkpto 0¤·
In the course of design and development of these transistors, mgistancc avalanche br akdo n it pe dg t b
several of their characteristics have been studied in detail. mute michthmugh V itc W VO ag ’ an S°um°` °`Su `
Three major areas of study have been l) effects of device pro- TMPO timizmon gogggiue in des. nm these devices is as
ccssing on thmshold v°1tag°’ 2) cuncntwoltagc behavior` and follows pFirst selectpthe highest epitfxialiayer concentration
3) breakdown voltage. Work in the first two areas has already Nd to' mininjiizc Onqcsistamc consistent with the desired
Pun r°p°¥t°d [2] ’. [3]* TM pmp°S° °f tim °°¤°Sp°“d°n°° avalanche breakdown voltage (200 V in our case). Using this
is to describe a particular set of tradeoffs which relate threshold value for N the net peak impurity concentration inthe chmmci
voltage to the primary junction breakdown mechanisms in the N (mu) Ifeccssary to prevent s0m_ce__dl_ain punchthmugh can
high-voltage DMOS structure. “ .
A cross-sectional view of the type of device being considered ;§n;l£iun?tt€;;e;?i;i; Eggggzhgxxeé ;°;€;}5iaiEg°I%i1X:ngm??g;
in this correspondence is shown inFig. l. This device is capable N 8 minimum epitaxiai thickness to prevcni sOm_ce_i’0_sub_
of switching 200-V peak-to-peak analog signals with peak cur- Sigue pumhthmugh can be caicuiatcd
rents on the order of 0.3 A [4]. The overall dimensions of the '
device are roughly 570 um by 470 um. The channel width is
2040 pm and channel length is approximately 3 pm. Some of H- PUNCHTHROUGH BREAKDOWN BETWEEN SOURCE
the other important physical parameters are AND DRAIN V _ _ . .4 ·r-·
1) P- Substintc rcsisiivity i0_20 Q . cm Punchthrough breakdown can occur whenever the depletion
2) n- cpicnxini icsisiiviiy S_7 Q . cm layer of one junction spreads until it reaches the idepletton
3) cniinxini thickncss 25_30 mn region of another junction [5]. One of the most important
4) t i · i· d th 5 punchthrough mechanisms in high-voltage DMOS devices is that
5) 5hciiOi;i1iJ;?§;%2pi? 4_l;J;m of the channel diffusion under the gate. Although the deple-
6) n+ scin.cc_dicin junction depth i_5 nin tion layer of the channel—dra.in junction spreads primarily into
7) gctc cxidc thickness 0.3 um the more lightly doped drain drift region, the shortness of the
8) ficid cxidc thickncss i_5 [hn channel raises the possibility of punchthrough due to the small
_ amount of spreading of the depletion layer into the more
The Pf¢V1¤¤S W01’k 01* thI¢Sh¤ld V0}t¤8¤ [2] Showed that **16 heavily doped channel region. An approximate calculation of
threshold voltage is. determined by the maximum net surface this punchth]-Ough voltage can be madc by assuming c hncai-
impurity concentratron m the channel N, (max). _The Study of distribution of impurity in the channel diffusion and uniform
¤¤1`f¢¤f vvltasc b¤h¤V10f [3] Sh¤W¢d that 0¤·¤'¤$15t¤¤¤¤ of tht? distribution in the epitaxial layer. Assuming complete ioniza-
tion, the electric field and voltage drop across the depletion
Manuscript received May 2, 1977; revised May 14, 1978. This work layer cim be calculated by solvmg Poissonk cquatwn m one
was performed in part under the auspices of the U.S. Energy Research d1m°¤”°n· l _
and Development Administration under Contract W-7405-Eng-48. It The total P“¤chthT°uSh VOREEE is Ewen by
was also supported in part by NIH under Grant 1 P01GM1 17940-5 and N ) N2
in part by NSF under Grant Eng. 74-18419. VR = EL JSIBEL + -_“ (ma.._x) xi (1)
M. D. Pocha is with the Lawrem; Livermore Laboratory, University 6, 6 8Nd A'
of California, P.O. Box 808, Ll56, Livermore, CA 94550. _
J. D. mummer and J. D. Meindl are with sunrcra Electronics Lab- Equation (1) shows the f¤11¤wins= 1) The punchthmush
oratory, Stanford,CA 94305. voltage is proportional to the square of the channel length
0018-9383/78/1100-1325 $00.75 @1978 IEEE

Case 1:04-cv-01371-JJF Document 173-9 Frled O1/23/2006 Page 3 of 4
1326 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-2s, NO. 11, NOVEMBER 1978
· The experimental measurements for the VT = 6 V case are
—- cqrwaaraa somewhat lower than the theoretical results, as the breakdown
,00 "°" E"°°"”’°"'°' occurs due to avalanche in this case and is influenced by sur-
rermcr. r...r.r.,W. mr, fm effects-
> zao
lr 225 TO" VT = <> III. PUNCHTHROUGH BREAKDOWN BE·rwEEN Souacra
2 VT = 6 AND SUBSTRATE
9 |··O··i VT = 4 _ _
sr ,00 The source·to-substrate punchthrough rs of importance
jg •. when the DMOS device is used as an analog multiplexer, or in
.§ any application in which the source is biased above the p`
,5 25 •- substrate. The punchthrough is actually from the p" contact
' to substrate, but the source is generally connected to the p+
contact to prevent back-gate bias effects. This punchthrough
3 r 2 3 4 5 6 7 can occur when both source and drain are at a high positive
Ch I R rh (X potential with respect to the substrate. As the potential dif-
°""° °"° A) " ""` ference is increased, the depletion layer of the substrate-to-
Fig. 2. Calculated and measured source—drain punchthrough voltage epitaxy junction spreads upward into the epitaxial region and
fm ml ¤rf¢ P¥°m° and 54-7- ' cm ¤Pil¤Xi¤l ]¤Y¢1‘· downward into the substrate. The nearest junction is the p+
contact diffusion so that, when the depletion layer reaches
2 _ _ this junction’s depletion region, punchthrough occurs.
xA· 2) Tho Wmomtor of (1) oontams N4 (maX)· Yvhlch ]"'° Again the width of this depletion layer can be calculated
recall determines the threshold voltage [2]. Devices with by serving peieeeiys equation for the required voltage. The
higher threshold voltage will, therefore, have higher punch- result for our ease Nd = I X 1015 em-3 and 200 V is rr der,ie_
through voltages- 3) Tho denominator of VR contains Mb tion layer width in the epitaxial layer of 18.0 pm. Since the
the epitaxial concentration. Devices with lower Gpitlviisl P" Contact is approximately S pm deep, the total epitaxial
dolmlg wm- to°’of°’°» hav? higher Ponfihthrough "olt3»B°$· layer thickness must be over 23 pm. To allow some tollerance
The aPPT°X1mat€ imP“¤tY distribution used to d°V°loP tho for processing variations, the epitaxial layer is targetted at
analytical expression in (1) gives an intuitive understanding 25-30 HTTL
of the relationship between the channel length, the maximum
doping concentration, and the breakdown voltage. Based on W' DISCUSSION OF RESULTS
theoretical work by Kennedy and O’Brien [6], the lateral The results of the preceding discussions can be summarized
impurity profile in the channel diffusion is thought to be more as follows. Study of threshold voltage indicates that it is
accurately described by the complementary error function determined by the maximum net impurity concentration in
(erfc) [2]. Fig. 2 shows the results of breakdown-voltage the channel region NA (max) and that processing variation
calculations obtained by numerically integrating the more effects can be minimized by a sufficiently long channel length
accurate impurity profiles. In this figure, the source-to-drain and a minimum value of threshold voltage [2]. Study of
punchthrough voltage is plotted on a square-root scale versus source-drain punchthrough shows that it is also a function of
channel length with threshold voltage and epitaxial concentra- Na (max) resulting in a lower bound for threshold voltage for
tion as parameters. The threshold voltage was calculated for a a given breakdown and epitaxial layer concentration Nd. How-
3000-A gate oxide necessary for 200-V gate-to-source dielectric ever, by reducing Nd, the lower bound on the threshold voltage
breakdown. The horizontal line at the top of the figure is tL1e can also be reduced. Nd relates source-drain breakdown to
limiting avalanche breakdown voltage of the drain chanr.el another punchthrough breakdown from source to substrate
junction calculated using a simple critical field model. Tae when the DMOS device is used as an analog multiplexer. The
diagonal lines are the punchthrough voltages. For example, in source-to-substrate punchthrough determines the thickness
Fig. 2 a device having 3-pm channel length and 1-V threshold of the epitaxial material required for a given breakdown vol-
voltage will exhibit punchthrough at 25-V drain-to-source and tage. This required epitaxial layer thickness increases as Nd
a threshold voltage of over 4 V is necessary to increase the decreases. The increase in epitaxial layer thickness requires
punchthrough voltage to greater than 200 V. Equation (1) deeper isolation diffusions, therefore, increasing the device
shows that punchthrough voltage increases as the impurity size and processing time.
concentration of the epitaxial layer decreases. intuitively, this The increased size and processing time are, however, minor
is because the depletion layer spreads more into the 11 region considerations, since the major effect of reducing Nd is on
when it is more lightly doped. If (1) is used directly to make the electrical properties of the DMOS transistor. ln the pre-
plots similar to Fig. 2, the calculated punchthrough voltages viously published discussion of the current-voltage behavior of
appear 20 to 50 percent higher than those in Fig. 2 for a given these devices it was shown that the high-voltage DMOS struc-
channel length and threshold voltage. ture could be modeled as an n-channel enhancement MOSFET
Experimental measurements of punchthrough voltage have in series with a fixed resistor [3]. The value of this series
been made on several devices with different threshold voltages. resistance is inversely proportional to Nd since it physically
Their approximate channel lengths were then obtained from arises from the n" drift region between the channel and the
the impurity distributions. The results, plotted on Fig. 2, are drain n* diffusion. Therefore, decreasing Nd results in an in-
in good agreement with the calculations except for the VT == 6 crease in the on—resistar1ce of the DMOS device. The effect of
V value discussed below. These experimental devices exhibit Nd on source-drain punchthrough and minimum threshold
the classic "soft breakdown" characteristic associated wi.th voltage is not as pronounced, and therefore Nd should be
punchthrough at low values of threshold voltage and "hard made as large as possible. The upper limit of Nd is determined
breakdown" associated with avalanche at high threshold voltage by avalanche breakdown of the p-type bulk channel diffusion
[7]. Also, in Fig. 2 is plotted a line for the depletion layer of to the n" epitaxial layer. Fig. 2 shows that the theoretical
the more heavily doped pl source contact diffusion (Fig. l) avalanche breakdown for this junction with Nd = 1 X 1015
showing that the depletion layer spreads less than 1 um irto cm'° is about 280 V implying that a higher value of Nd could
this diffusion before avalanche breakdown occurs. be used. However, dueto surface effects, the actual breakdown

Case 1:04-cv-01371-JJF Document 173-9 Filed O1/23/2006 Page 4 of 4
CORRESPONDENCE 1327
voltage of these junctions range from 225 to 250 V. Thus the N *
target value Nd = 1 X 1015 cm`3 is approximately the maxi- I
mum epitaxial layer concentration for 200-V operation allow- l I°’ s rw
ing for some variations i11 processing. _ ' 'Af
‘*· CONC 11, 1,,%
0
Tradeoffs between threshold voltage, punchthrough voltage, l XH
avalanche breakdown voltage, and on-resistance in the high- jj; rr
voltage DMOS structure have been discussed. It is shown that r XN _x_ —-1 Lx]
a maximum epitaxial layer concentration (to minimize on I I I
resistance) of 1 X 1015 cm`3 is consistent with a 200-V ava-
lanche breakdown voltage requirement. This value of Nd leads . .... - .....,.............. -
to a minimum threshold voltage constraint of 4 V to obtain a N+ `_ Ns
drain-to~source punchthrough voltage of greater than 200 V.
Finally, an epitaxial layer thickness greater than 23 um is N+
necessary for source-to-substrate punchthrough voltage greater _ + + + ____
than 200 V when the device is used as an analog multiplexer. P18- 1- P ‘¤‘¤ di°d° with d°°P 1* 1$°1¤11°¤ d1f1`“$1°¤·
While these results are based on a 200-V breakdown con-
straint, the calculations are sufficiently general to apply to layer on an n+ substrate It has been Shown that in both cases
°th°I deslgm as w°lI‘ the additional current components can be an appreciable frac-
tion of the normal "vertical" current due to injection and re-
REFERENCES combination within the n epitaxial layer between the p+-n and
(1] J. D. Plummer, J. D. Meindl, and M. G. Maginness, "Anu1trasonlc the n·n* junctions. In this correspondence, we give results
imagine systems for rea! time cardiac imaging? in Dig. Im. Solid- which enable prediction of the comer current when the rec·
xg; giwgfs Olggligdelphia. PA. Feb- 1974). PP- 162-1637 tangular diode is surropnded by an n* isolation diffusion cx-
· °- ‘ - t d' , ' h ff f
121 gat; ggiggélmgel;gmmumbg;;;;·;;st;g;1;_»;;<;g vggyxilggizisfsngcoftnsggitiggfarrgifr?n:cf1i:ré;g::r:1f;;*
M,. Eremnpevrcel, ...1. ann, rz, pp. 778-784, isn. dgffuglan 1; ¤<2¤=;¤e·=d— The *¤¤h···¤¤~= e w¤*=lv um m HL
[3] M. D. Pocha and R. W. Dutton, "A computer-aided design model S mc mes M B0 ation p“rp°s°s‘
for high voltage double diffused MOS (DMOS) transistors," IEEE
J: semisme cimuanvel.sc-11,nc.s,pp.71s-726,1976. N· CALCULATION °F THE CORNER AND
[4] J. 1>. Plummer and J. D. Meindl, ··A monolithic 200 volt cmos LATERAL CURRENTS
anal§59s1§¥§hB’ [Egg] Solid-State cl}‘Clll'fS, vol. SC-ll, no. 12, Referring to pig_ 1, the Phu junction depth is X], the n.n;
in $E‘s,Yc}l.;7ix;rZ§i7ci6a7a rgchmzagy of Semiconductor Devices. l§g‘,j§§,f, Q; gf :d",;§@‘j,° §§°§Off,"i,f§§?§;°;,f,§‘;*,,f,*§,° ‘§§‘,,
New or: iley,19 7,p.20. . . . . . . . .' .
[6] D. P. Kennedy and R. R. O‘Brien, *‘Ana1ygi_; Orme jynpugity atom $1}1’1P111Yt1¤8 ¤S¤¤ml1110l1 15 rhade fhat the n-n" 1solat1on1sequ1-
distribution near the diffusion mask for a planar p-n junction," dlstant mm th° P 'n Jumitlon at an p°mts+Nl°ng the P°mph°rY
j3M_]__ VOL 9, pp_ 179-186, May 1g55_ and that the hole current is zero at the n-n interface.
[7] A, s. Grove, 1967, For an injected carrier concentration p(0) at every point
along the periphery and in the bulk, at the depletion layer
boundary, the vertical current is given by
Comer Currents in p"-n-n" Diodes with 11* Isolation Iv = GBLP (0) (Xepi ‘ X;)/'T (1)
D1ff“S1°nS where 1· is the minority carrier lifetime in the epitaxial layer
DAVID J. Roursrorv AND Monnnan H. atsain ;"§if’§£;'f, f;i;‘:“‘° °h“'“°‘ B ““° L m ‘h° d‘m°'"“°““ °f 1h°
The current diffusing laterally from the junction is given by
Abstract-The magnitude of corner currents in rectangular diffused _
pl-n-n* diodes with deep n* isolation diffusions is discussed. Curves are 1181 ' 2413 + L) P (0) X¤P1(DP [LP) tanh 1(X N ` X/)/LP]
given to illustrate the importance of this current in diodes and HL (2)
stm°““°S' where L P = D,·r.
I_ INTRODUCTION For the case where X N - X] << Lp, (2) simplifies to
Recent papers [1] , [2} give results which enable prediction Im = 2q (B +L) p(O) Xgp,(XN — X ,)/1. (3)
of radial currents from circular diodes or comer currents from In Order t nl I t th t t 1 th
rectangular diodes made by one p* diffusion into an epitaxial continuity Bgugtigg gnccyugggggzggglgllaiege mus so vc c
d’ 1 rz
Manuscript received January 31, 1978; revised May 29, 1978. This é, + — -11 - % = 0 (4)
work was supported by a Grant from the National Research Council of dr V dT Lp
Canada. , . _ _
D. J. Roulston is with the Electrical Engineering Department, Univer- Phe bgundm-X °93*d1¤9¤1 b°mg Ig = 0 at " = XN (assummg an
my of wam.1O0’ w,,wdOO_ OM N2L_3G1, Cam,da_ rdeal reflecting n-n rnterface , and hence dp/dr = 0 at r =
M. H. Elsaid was with the Electrical Engineering Department, Univer- XN- Th° 8°¤°T¤1 $°111t1¤¤ te 11115 ¤¢l¤¤110!1 1¤V01V€S 8 linear
sity of Waterloo, Waterloo, Ont. N2Lr3G1, Canada. He is now with the 90111191-¤8110I\ of the modified Bessel function of the first kind
Electrical Engineering Department, Ain Shams University, Cairo, Egypt. of order zero and the modified Bessel function of the third
0018-9383/78/l100-1327500.75 © 1978 IEEE