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(12)
United States Patent
Ahn et al.
THIN-FILM TRANSISTOR AND METHOD OF MAKING SAME Inventors: Byung-Chul Ahn, Kumi-shi (KR); Hyun-Sik Seo, Anyang-shi (KR) Assignee: LG. Philips LCD. Co., Ltd., Seoul (KR) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. This patent is subject to a terminal disclaimer. Appl. No.: 101872,527 Filed: Jun. 22, 2004 Prior Publication Data US 200410229413 A1 Nov. 18. 2004
EP
(10) (45)
Patent NO.: US 7,176,489 B2 Date of Patent: *Feb. 13,2007
(52) U.S. C1. ............................ 257159; 257157; 257166; 257172; 257173; 2571291; 2571359 (58) Field of Classification Search .................. 257157, 257159, 66, 73, 359, 72, 291 See application file for complete search history. (56)
4,220,706 A
References Cited U.S. PATENT DOCUMENTS
911980 Spak
.......................... 4301318
(Continued) FOREIGN PATENT DOCUMENTS
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(Continued) OTHER PUBLICATIONS
"Low Cost, High Display Quality TFT-LCD Process", Society for Information Display, EuroDisplay 96, Proceedings of the 16th International Display Research Conference, Oct. 1, 1996, 591-594.
(Continued) Primary Examiner-Ida M. Soward (74) Attorney, Agent, or Firm-Birch, Stewart, Kolasch and Birch, LLP (57) ABSTRACT
Related U.S. Application Data Division of application No. 101377,732, filed on Mar. 4, 2003, now Pat. No. 6,815,321, which is a division of applicationNo. 101154,955, filed on May 28,2002, now Pat. No. 6,548,829, which is a continuation of application No. 091940,504, filed on Aug. 29, 2001, now abandoned, which is a division of application No. 091243,556, filed on Feb. 2, 1999, now Pat. No. 6,340,610, which is a division of application No. 081918,119, filed on Aug. 27, 1997, now Pat. No. 5,905,274. Foreign Application Priority Data : a . 4, 1997 (KR) ................................... 97-07010 (2006.01) (2006.01) (2006.01) (2006.01) (2006.01)
Int. C1. HOIL 29/04 HOIL 29/10 HOIL 31/036 HOlL 31/0376 HOIL 31/20
A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being A wider than the second metal layer by 1 to 4 p. method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
3 Claims, 6 Drawing Sheets
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US 7.176.489 B2
Page 2 U.S. PATENT DOCUMENTS
5.036. 370 5.132. 745 5.156. 986 5.162. 933 5.191.453 5.349. 205 5.428. 250 5.464. 500 5.644. 146 5.686. 749 5.721. 164 5.731. 216 5.808. 336 5.808.595
A A A A A A A A A A A A A A
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711991 711992 1011992 1111992 311993 911994 611995 1111995 711997 1111997 211998 311998 911998 911998
Miyago et al ................ 257172 Kwasnick et a1........... 2571412 Wei et a1.................... 4381159 Kakuda et al ................ 349146 Okumura ..................... 349147 Kobayashi et al ............ 257159 Ikeda et a1.................. 3491147 Tsujimura et al ............. 216134 Arai et a1..................... 257166 Matsuo ....................... 2571316 Wu ............................ 4381159 Holmberg et al ............. 438130 Miyawaki ................... 2571315 Kubota et a1................. 345192 Yamamoto et a1.......... 3491152 Lee ............................. 349142 Sin et al ..................... 2571347 Masuda et al .............. 4381406 Miyazaki et a1............ 2571347 Seo ............................. 257172 Seo ............................ 4381149
409753 1 1120068 1222448 3114028 5315615 5343683 637311 6104241 06281954 7077695 08095083 A 8254680 954593 9206504
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311982 511989 911989 511991 1111993 1211993 211994 411994 1011994 311995 411996 1011996 211995 411992
OTHER PUBLICATIONS
"Hilllock-Free Al-Gate Materials Using Stress-Absorbing Buffer Layer for Large Area AMLCDs" Society for information Display 96 Digest. pp . 341.344. 1996. "Wet Etchant for Molybdenum Having High Selectivity Against Aluminum". IBM Technical Disclosure Bulletin. vol . 35. No . 3. Aug . 1. 1992. pp . 205-206. XP 000326238 . AT Patent Abstracts of Japan. vol . 9. No . 315 [E-3651 and Japan 60-149173 (Hitachi) . AU Patent Abstracts of Japan. vol . 5. No . 197 [E-861 and Japan 56-118370 (Cho Lsi Gijutsu) . "Pure A1 and Al-Alloy Gate-Line Processes in TFT-LCDs". Samsung Electronics Co.. Ltd.. Kiheung. Korea. C.W. Kim et al.. SID 96 Digest. pp . 337-340 .
FOREIGN PATENT DOCUMENTS
EP EP EP GB GB GB
9206497 06023 15 0812012 2253742 2254187 2307597
411992 711993 1211997 911992 911992 511997
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US 7,176,489 B2
1
THIN-FILM TRANSISTOR AND METHOD OF MAKING SAME
2
Referring to FIG. lA, aluminum is deposited on a substrate 1 to form a first metal layer 13. A first photoresist 15 1 is deposited on the first metal layer 13. The first photoresist This application is a divisional of application Ser. No. 15 is exposed and developed so as to have a certain width w l 101377,732 filed on Mar. 4, 2003 now U.S. Pat. No. 6,815, 5 extending along the first metal layer 13. 321, which is a divisional of application Ser. No. 101154,955 Referring to FIG. l B , the first metal layer 13 is patterned filed on May 28, 2002 now U.S. Pat. No. 6,548,829, which via wet etching using the first photoresist 15 as a mask so is a continuation of abandoned application Ser. No. 091940, that the first metal layer 13 has a certain width w l . After the first photoresist 15 is removed, a second metal layer 17 is 504, filed onAug. 29,2001, which is a divisional application 1 under 37 C.F.R. § 1.53(b) of patented prior application Ser. 10 formed by depositing Mo, Ta, or Co on the substrate 1 so as to cover the first metal layer 13. A second photoresist 19 No. 091243,556 (U.S. Pat. No. 6,340,610 B1) filed on Feb. is then deposited on the second metal layer 17. The second 2, 1999 (Issued on Jan. 22, 2002), which is a divisional photoresist 19 is exposed and developed so as to have a application under 37 C.F.R. § 1.53(b) of patented prior application Ser. No. 081918,119 (U.S. Pat. No. 5,905,274) certain width w2 extending along the second metal layer 17 filed on Aug. 27, 1997 (Issued on May 18, 1999), the entire 1s and located above the first metal layer 13. contents of which are hereby incorporated by reference and Referring to FIG. lC, the second metal layer 17 is patterned via a wet etching process using the second phofor which priority is claimed under 35 U.S.C. § 120; and this application claims priority of Application No. 97-07010 toresist 19 as a mask such that the second metal layer 17 has a certain width w2 which is narrower than the width w l of filed in Korea on Mar. 4, 1997 under 35 U.S.C. § 119. 20 the first metal layer 13. After formation of the gate 21, the BACKGROUND OF THE INVENTION second photoresist 19 is removed. Thus, the patterned first and second metal layers 13 and 1. Field of the Invention 17 form a gate 21 having a double-layered metal structure The present invention relates to a thin-film transistor of a that provides double step difference between the doubleliquid crystal display and, more particularly, t~ a thin-film 25 layered metal gate structure 21 and the substrate 11. The transistor having a gate including a double-layered metal formation of the gate 21 as described above and shown in structure and a method of making such a double-layered FIGS. 1A-IF requires the use of two photoresists 15,19 and metal gate. two photoresist steps. 2. Discussion of Related Art In the gate 21, shown in FIG. lC, the second metal layer An LCD (Liquid Crystal Display) includes a switching 30 17 is preferably centrally located on the first metal layer 13. device as a driving element, and a pixel-arranged matrix Although there is no specific information available regardstructure having transparent or light-reflecting pixel elecing a relationship of w l to w2 of this related art method, trodes as its basic units. The switching device is a thin-film based on their understanding of this related method resulting transistor having gate, source and drain regions. in the structure shown in FIG. lC, the inventors of the The gate of the thin-film transistor is made of aluminum 35 invention described and claimed in the present application to reduce its wiring resistance, but an aluminum gate may assume that the width difference wl-w2 between the first cause defects such as hillock. and second metal layers 13 and 17 is larger than or equal to A double-layered metal gate, i.e., molybdenum-coated 4 pm, that is, wl-w224 pm. aluminum gate is considered as a substitute for the alumiReferring to FIG. ID, a first insulating layer 23 is formed num gate to overcome the problem of the hillock. 40 by depositing silicon oxide SiO, or silicon nitride Si,N, as To fabricate a double-layered gate, metals such as alumia single-layered or double-layered structure on the gate 21 num and molybdenum are sequentially deposited, followed and substrate 11. Semiconductor and ohmic contact layers by a patterning process carried out via photolithography to 25 and 27 are formed by sequentially depositing undoped form resulting metal films which have the same width. polycrystalline silicon and heavily doped silicon on the first Although the double-layered gate is desirable to overcome 45 insulating layer 23. The semiconductor and ohmic contact the problem of hillock, the resulting deposited metal films layers 25 and 27 are patterned to expose the first insulating forming the double-layered gate are so thick that a severe layer 23 by photolithography. single step is created by a thickness difference between the Referring to FIG. l E , conductive metal such as aluminum metal films and a substrate, thereby causing a single step is laminated on the insulating and ohmic contact layers 23 difference between the substrate and the double-layered gate 50 and 27. The conductive metal is patterned by photolithogwhich deteriorates the step coverage of a later formed gate raphy so as to form source electrode 29 and a drain electrode oxide layer. The source and drain regions formed on the gate 31. Aportion of the ohmic contact layer 27 exposed between oxide layer may have disconnections between areas of the the source and drain electrodes 29 and 31 is etched by using the source and drain electrodes 29 and 31 as masks. source and drain regions which are overlapped and nonReferring to FIG. IF, silicon oxide or silicon nitride is overlapped with the gate, or electrically exhibit short circuits 55 as a result of contact with the gate. deposited on the entire surface of the structure to form a According to another method of forming the gate, each of second insulating layer 33. The second insulating layer 33 is etched to expose a designated portion of the drain electrode the metal layers of A1 and Mo form a double step difference with the substrate so as to improve the step coverage of the 31, thus forming a contact hole 35. By depositing transpargate oxide layer. 60 ent and conductive material on the second insulating layer 33 and patterning it via photolithography, a pixel electrode FIGS. 1A through 1F are diagrams illustrating the process for fabricating a thin-film transistor of a method which is 37 is formed so as to be electrically connected to the drain related to the invention described and claimed in the present electrode 31 through the contact hole 35. According to the method of fabricating a thin-film tranapplication. The method shown in FIGS. 1A-1F is not believed to be published prior art but is merely a recently 65 sistor as described above and shown in FIGS. 1A-IF, discovered method related to the invention described and respective first and second metal layers are formed through claimed in the present application. photolithography using different masks so as to form the
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gate with a double-layered metal structure, resulting in double step differences between the gate and substrate. As a result of the double step difference between the gate 1 21 and the substrate 1 shown in FIG. l C , a hillock often occurs on both side portions of the first metal layer 13 which have no portion of the second metal layer 17 deposited thereon when the first metal layer 13 is wider than the second metal layer 17 as in FIG. 1C. Another problem with this related art method is that the process for forming a gate is complex and requires two photoresists 15, 19 and two steps of deposition and photolithography. As a result, the contact resistance between the first and second metal layers may be increased. Another related art method of forming a double metal layer gate structure is described in "Low Cost, High Quality TFT-LCD Process", SOCIETY FOR INFORMATION DISPLAY EURO DISPLAY 96, Proceedings of the 1 6 Inter~ ~ Research Birmingham, Oct. 996, pages 591L594. One page 592 of this publication, a method forming a gate structure includes the process of depositing two metal layers first and then patterning the two metal layer to thereby eliminate an additional photoresist step. However, with this method, process difficulties during the one step photoresist process for forming the double metal layer gate resulted in the top layer being wider than the bottom layer causing an overhang condition in which the top layer the bottom layer. This difficulty may result in poor step coverage and disconnection, hi^ problem was solved by using a three-step etching process in which the photoresist had to be baked before each of the three etching steps to avoid lift-off or removal of the photoresist during etching. This three-step etching process and required baking of the photoresist significantly increases the complexity and steps of the gate forming method. SUMMARY OF THE INVENTION To overcome the problems discussed above, the preferred embodiments of the present invention provide a thin-film transistor which prevents a hillock and deterioration of step coverage of a later formed gate oxide layer on a double metal layer gate. The preferred embodiments of the present invention also provide a method of fabricating a thin-film transistor that simplifies the process for forming a double metal layer gate. nepreferred embodiments of the present invention further provide a method of fabricating a thin-film transistor that reduces the contact resistance between the first and second metal layers constituting a gate. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as, the appended drawings. To achieve these and other advantages and in accordance with the purpose of the preferred embodiments of the present invention, as embodied and broadly described, a thin-film transistor preferably comprises a substrate, and a gate including a double-layered structure of first and second metal layers disposed on the substrate, the first metal layer being wider than the second metal layer by about 1 to 4 pm, and a method of making such a thin-film transistor preferably comprises the steps of depositing a first metal layer on a substrate, depositing a second metal layer directly on the
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first metal layer; forming a photoresist having a desired width on the second metal layer; patterning the second metal layer via an isotropic etching using the photoresist as a mask; patterning the first metal layer via an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have a desired width, thus forming a gate having a laminated structure of the first and second layers; and removing the photoresist. These and other elements, features, and advantages of the preferred embodiments of the present invention will be apparent from the following detailed description of the preferred embodiments of the present invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
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The accompanying drawings, which are included to provide a further of the invention and are incorporated in and constitute a part of this specification, illustrate preferred embodiments of the invention and together with the description serve to explain the principles of the invention, in which: FIGS. 1A through 1F are diagrams illustrating a process for fabricating a thin-film transistor according to a method of the related art; FIG. 2 is a top view of a thin-film transistor according to a preferred embodiment of the present invention; FIG. 3 is a cross-sectional view taken along line 111-111 of FIG. 2; and FIGS. 4A through 4F are diagrams illustrating a process for fabricating a thin-film transistor of preferred embodiments of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Reference will now be made in detail to preferred embodiments of the present invention, of which are illustrated in the accompanying drawings, FIG. 2 is a top view of a thin-film transistor according to a preferred embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 111-111 of FIG. 2. The thin-fi1m a gate 49 having a double-layered structure of a first layer 43, a second metal layer 45 disposed on a substrate 41, a first insulating layer 51, a second insulating layers 61, a semiconductor layer 53, an ohmic contact layer 55, a source electrode 57, a drain electrode 59, and a pixel electrode 65. The gate 49 has a double-layered structure including the first and second metal layers 43 and 45 disposed on the substrate 41. The first metal layer 43 is preferably formed from a conductive metal such as Al, Cu, or Au deposited to have a certain width w l . The second metal layer 45 is preferably formed from a refractory metal such as Mo, Ta, or Co deposited to have a certain width w2. The present inventors have discovered that a relationship between the width of the first metal layer and the width of the second metal layer of a double metal layer gate electrode is critical to preventing deterioration of step coverage of a later formed gate oxide layer in such a structure having a double step difference between the substrate and the gate. More specifically, the present inventors determined that a structure wherein the first metal layer 43 is wider than the second metal layer 45 by about 1 to 4 pm, for example, 1 pmewl-w2e4 pm, provides maximum prevention of dete-
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rioration of step coverage of a later formed gate oxide layer respectively, by means of sputtering or chemical vapor in such a structure having a double step difference between deposition (hereinafter, referred to as CVD) without breakthe substrate and the gate. ing a vacuum state. As a result, the contact resistance To achieve the best results, the second metal layer 45 is between the first and second metal layers 43 and 45 is preferably positioned substantially in the middle of the first 5 reduced. metal layer 45, so that both side portions of the first metal According to the preferred embodiments of the present layer 43 which have no portion of the second metal layer 45 invention, a single photoresist step is used to pattern both the disposed thereon have substantially the same width as each first metal layer 43 and the second metal layer 45 simultaother. The width of each of the side portions is preferably neously. In the single photoresist step, a photoresist 47 is l o deposited on the second metal layer 45 and then the photolarger than about 0.5 pm but less than about 2 p. The first insulating layer 51 is preferably formed by resist 47 is patterned through exposure and development to have the width w l on a designated portion of the second depositing single layer of silicon oxide SiO, or silicon metal layer 45. nitride Si3N4 on the substrate including the gate 49. The semiconductor and ohmic contact layers 53 and 55 Referring to FIG. 4B, the second metal layer 45 is are formed on the portion of the first insulating layer 51 1s patterned with an etching solution preferably prepared with corresponding to the gate 49 by sequentially depositing a mixture of phosphoric acid H3P04,acetic acid CH,COOH undoped amorphous silicon and heavily doped amorphous and nitric acid HNO,, by means of a wet etching using the silicon and patterning the two silicon layers. The semiconphotoresist 47 as a mask. Because the portion of the second ductor layer 53 is used as the active region of an element, metal layer 45 covered with the photoresist 47, as well as, thus forming a channel by means of a voltage applied to the 20 exposed side portions of the second metal layer 45 are gate 49. The ohmic contact layer 55 provides an ohmic isotropically etched, the second metal layer 45 is preferably contact between the semiconductor layer 53 and the source patterned to have the width w2 which is narrower than the and drain electrodes 57 and 59. The ohmic contact layer 55 width w l of the photoresist 47 which is the same as the is not formed in the portion that becomes the channel of the width w l of the first metal layer 43, that is, about 1 25 pmewl-w2e4 pm. Each side portion of the second metal semiconductor layer 53. The source and drain electrodes 57 and 59 are in contact layer 45 preferably has a width larger than about 0.5 pm and with the ohmic contact layer 55, and each electrode 57, 59 less than about 2 pm. That is, the two side portions of the extends to a designated portion on the first insulating layer second metal layer 45 covered with the photoresist 47 are 51. preferably etched to have substantially the same width as The second insulating layer 61 is formed by depositing 30 each other. The lateral surfaces of the second metal layer 45 insulating material such as silicon oxide SiO, silicon nitride are preferably etched to have a substantially rectangular or Si3N4to cover the source and drain electrodes 57 and 59 and inclined shape. the first insulating layer 51. The second insulating layer 61 Referring to FIG. 4C, the first metal layer 43 is patterned on the drain electrode 59 is removed to form a contact hole via dry etching having anisotropic etching characteristic 63. The pixel electrode 65 is formed from transparent and 35 such as reactive ion etching (hereinafter, referred to as RIE) by using the photoresist 47 as a mask. When etching the first conductive material such as IT0 (Indium Tin Oxide) or Tin oxide SnO,, so that it is connected to the drain electrode 59 metal layer 43 other than the portion of the layer 43 covered through the contact hole 63. with the photoresist 47, the first metal layer 43 preferably In the first and second metal layers 43 and 45 constituting has the same width w l of the photoresist 47. Thus, patternthe gate 49, each side portion of the first metal layer 43 40 ing of the first and second metal layers 43, 45, respectively, having no portion of the second metal layer 45 thereon has only requires two etching steps and does not require baking of the photoresist before each step of etching. Also, the a width that is preferably larger than about 0.5 pm and less Because the first metal layer 43 is wider relation between the first and second metal layers 43 and 45 than about 2 p. than the second metal layer 45 by about 1.0 pm to 4.0 pm, also may be represented by about 1 pmewl-w2e4 pm. The first and second metal layers 43 and 45 resulting form double step differences determined according to the rela- 45 tionship between the width of the first metal layer and the the single photoresist step process described above form a width of the second metal layer are formed between the gate gate 49 having a double-layered metal structure. The gate 49 49 and substrate 41. The double step differences determined has the second metal layer 45 positioned substantially in the according to the novel features of the preferred embodimiddle of the first metal layer 43 so that the each side portion ments of the present invention prevent deterioration of the 50 of the first metal layer 43 having no second metal layer 45 thereon is wider than about 0.5 pbut narrower than about coverage of the first insulating layer 51 which deterioration 2 pm. The photoresist 47 remaining on the second metal occurs in prior art devices. The hillock in the first metal layer 43 is also avoidable because the width difference between layer 45 is removed after the two etching steps are comthe first and second metal layers 43 and 45 is between about pleted. 55 Referring to FIG. 4D, a first insulating layer 51 is formed 1 pm to 4 pm. FIGS. 4A through 4F are diagrams illustrating the process by depositing a single layer or double layers of silicon oxide SiO, or silicon nitride Si3N4on the gate 49 and substrate 41 for fabricating the thin-film transistor of the preferred by CVD. Because each side portion of the first metal layer embodiments of the present invention. 43 having no second metal layer 45 thereon is wider than 0.5 Referring to FIG. 4A, metal such as Al, Cu, or Au is deposited on a substrate so as to form a first metal layer 43. 60 pm, double step differences formed between the substrate A second metal layer 45 is formed from Mo, Ta, or Co and and gate can prevent the coverage of the first insulating layer deposited on the first metal layer 43 without performing a 51 from being deteriorated as in prior art devices. The masking step between the step of depositing the first metal hillock in the first metal layer 43 is also avoidable because layer and the step of depositing the second metal layer. The a width of a portion of the first metal layer 43 which is first and second metal layers 43 and 45 are sequentially 65 exposed is less than about 2 p. deposited so as to preferably have a thickness as large as Amorphous silicon which is undoped and heavily doped about 500-4000 Angstroms and 500-2000 Angstroms, amorphous silicon are sequentially deposited on the first
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insulating layer 41 by CVD, thus forming semiconductor and ohmic contact layers 53 and 55. The ohmic contact and semiconductor layers 55 and 53 are patterned by means of photolithography to expose the first insulating layer 51. Referring to FIG. 4E,conductive metal such as A1 or Cr is laminated on the insulating and ohmic contact layers 51 and 55 and patterned by photolithography to form source and drain electrodes 57 and 59. The ohmic contact layer 55 exposed between the source and drain electrodes 57 and 59 is etched by using the source drain electrodes 57 and 59 as masks. Referring to FIG. 4F, a second insulating layer 61 is formed by depositing insulating material such as silicon oxide or silicon nitride by CVD on the entire surface of the above structure. The second insulating layer is removed by photolithography to expose a designated portion of the drain electrode 59 and thus form a contact hole 63. Once transparent and conductive material such as I T 0 (Indium Tin Oxide) or Tin oxide SnO, is deposited on the second insulating layer 61 via sputtering and patterned by photolithography, a pixel electrode 65 is formed so that it is electrically connected to the drain electrode 59 through the contact hole 63. In another preferred embodiment of the present invention, the first and second metal layers 43 and 45 are first etched by means of a dry etching having anisotropic etching characteristic such as RIE by using the photoresist 47 as a mask. The gate 49 is formed by etching the second metal layer 45 under the photoresist 47 with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH,COOH and nitric acid HNO,. In still another preferred embodiment of the present invention, the gate 49 is formed through a single etching step process for etching the first and second metal layers 43 and 45 simultaneously and via a single etching step, where the second metal layer 45 is etched more quickly than the first metal layer 43 with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH,COOH and nitric acid HNO,. Because of the etching material and metals used for the first and second metal layers of the gate, only a single etching step is required. Despite the fact that a single etching step is used, it is still possible to obtain the
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relationship between the widths w l and w2 of the first and second metal layers described above. In this process, the first and second metal layers forming the gate 49 are formed and patterned with a single photo resist step as described above and a single etching step. As described above, in the preferred embodiments of the present invention, the first and second metal layers are sequentially deposited on the substrate without performing a masking step between the step of depositing the first metal layer and the second metal layer, followed by forming a photoresist that covers a designated portion of the second metal layer. In one preferred embodiment, the second metal layer is wet etched by using the photoresist as a mask but the first metal layer is dry etched. As a result, the double-metal gate is formed. In another preferred embodiment, a single etching step is used to form the double-metal gate wherein both the first metal layer and the second metal layer are wet etched, but the difference in etching rates of the first and second metal layers produces different etching affects which result in the desired double-step structure. While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
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What is is: A thin a substrate; and a double-layered metal gate having a first metal layer and a second metal layer thereon, a total width of the first metal layer being greater than a total width of the second metal layer by about 1 to 4 pm. 2. The transistor of claim 1, wherein the first metal layer has a first and second side portion being exposed from the second metal layer, each side portion being at least about 0.5 pm in width. 3. The transistor of claim 2, wherein each side portion of the first metal layer is less than about 2 pm in width.
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Exhibit B
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United States Patent
Ahn et al.
(10) (45)
Patent NO.: US 6,815,321 B2 Date of Patent: Nov. 9,2004
(54) (75) (73)
THIN-FILM TRANSISTOR AND METHOD OF MAKING SAME
Inventors: Byung-Chul Ahn, Kumi-shi (KR); Hyun-Sik Seo, Anyang-shi (KR) Assignee: LG. Philips LCD Co., Ltd., Seoul (KR) Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
EP EP EP EP
5,428,250 5,464,500 5,821,159 6,340,610
A 611995 Ikeda et al. A 1111995 Tsujimura et al. A * 1011998 Ukita ......................... 4381592 B1 * 112002 Ahn et al. .................. 4381158 0301571 9206497 0602315 0812012 211989 411992 711993 1211997
FOREIGN PATENT DOCUMENTS
( * ) Notice:
(List continued on next page.) OTHER PUBLICATIONS "Low Cost, High Display Quality TFT-LCD Process", Society for Information Display, EuroDisplay 96, Proceedings of the 16th International Display Research Conference, Oct. 1, 1996, 591-594. "Hilllock-Free Al-Gate Materials Using Stress-Absorbing Buffer Layer for Large Area AMLCDs" Society for information Display 96 Digest, pp. 341-344, 1996. (List continued on next page.) Primary ExaminerAong Pham Assistant Examiner-Wai-Sing Louie (74) Attorney, Agent, or F i r m a i r c h , Stewart, Kolasch & Birch, LLP (57)
(21) (22) (65)
Appl. No.: 101377,732 Filed:
Mar. 4, 2003 Prior Publication Data
US 200310164520 A1 Sep. 4, 2003
Related U.S. Application Data
(62)
Division of application No. 101154,955, filed on May 28, 2002, now Pat. No. 6,548,829, which is a continuation of application No. 091940,504, filed on Aug. 29, 2001, now abandoned, which is a division of application No. 091243, 556, filed on Feb. 2, 1999, now Pat. No. 6,340,610, which is a division of application No. 081918,119, filed on Aug. 27, 1997, now Pat. No. 5,905,274.
ABSTRACT
(30) (51) (52)
Foreign Application Priority Data Mar. 4, 1997 (KR) ........................................ 1997-7010 Int. CL7 ........................................ HOlL 2113205 U.S. C1. ....................... 4381592; 4381155; 4381481; 4381482; 4381483; 4381588 Field of Search ................................. 2571149, 158, 2571482, 588, 592 References Cited U.S. PATENT DOCUMENTS
4,220,706 5,036,370 5,132,745 5,156,986 5,162,933 A 911980 Spak A 711991 Miyago et al. A * 711992 Kwasnick et al. A 1011992 Wei et al. A 1111992 Kakuda et al.
(58) (56)
.......... 2571412
A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 pm. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
22 Claims, 6 Drawing Sheets
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FOREIGN PATENT DOCUMENTS
2253742 2254187 2307597 4097531 1120068 1222448 3114028 5315615 5343683 637311 6104241 06281954 7077695 8254680 911992 911992 511997 311982 511989 911989 511991 1111993 1211993 211994 411994 1011994 311995 1011996
OTHER PUBLICATIONS "Wet Etchant for Molybdenum Having High Selectivity Against Aluminum", IBM Technical Disclosure Bulletin, vol. 35, No. 3, Aug. 1, 1992, pp. 205-206, XP 000326238. AT Patent Abstracts of Japan, vol. 9, No. 315 [E-3651 and Japan 60-149173 (Hitachi). AU Patent Abstracts of Japan, vol. 5, No. 197 [E-861 and Japan 56-118370 (Cho Lsi Gijutsu). "Pure Al and Al-Alloy Gate-Line Processes in TFT-LCDs", Samsung Electronics Co., Ltd., Kiheung, Korea, C.W. Kim et al., SID 96 Digest, pp. 337-340. * cited by examiner
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FIG.1C
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FIG.4A
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Referring to FIG. l A , aluminum is deposited on a substrate 1 to form a first metal layer 13. A first photoresist 15 1 is deposited on the first metal layer 13. The first photoresist 1 5 is exposed and developed SO as to have a certain width w l This application is a divisional of application Ser. No. 101154,955, filed on May 28, 2002, now U.S. Pat. No. 5 extending along the first metal layer 13. 6,548,829 which is a continuation of abandoned application Referring to FIG. l B , the first metal layer 13 is patterned Ser. No. 091940,504, filed on Aug. 29, 2001, which is a via wet etching using the first photoresist 1 5 as a mask so divisional application under 37 C.F.R. §1.53(b) of patented that the first metal layer 13 has a certain width w l . After the prior application Ser. No. 091243,556 (U.S. Pat. No. 6,340, first photoresist 1 5 is removed, a second metal layer 17 is 610 B1) filed on Feb. 2, 1999 (Issued on Jan. 22, 2002):, 10 formed by depositing Mo, Ta, or Co on the substrate 1 so 1 as to cover the first metal layer 13. Asecond photoresist 19 which is divisional application under 37 C.F.R. §1.53(b) of patentedprior application Ser. No. 081918,119 (U.S. Pat. No. is then deposited on the second metal layer 17. The second 5,905,274) filed on Aug. 27,1997 (Issued on May 18,1999) photoresist 19 is exposed and developed so as to have a the entire contents of which are hereby incorporated by certain width w2 extending along the second metal layer 17 reference and for which priority is claimed under 35 U.S.C. 1s and located above the first metal layer 13. $120; and this application claims priority of Application NO. Referring to FIG, l C , the second metal layer 1 7 is 97-07010 filed in Korea on Mar. 4, 1997 under 35 U.S.C. patterned via a wet etching process using the second pho$119. toresist 19 as a mask such that the second metal laver 1 7 has a certain width w2 which is narrower than the width w l of BACKGROUND OF THE INVENTION 20 the first metal layer 13. After formation of the gate 21, the second photoresist 19 is removed. 1. Field of the Invention Thus, the patterned first and second metal layers 13 and The present invention relates to a thin-film transistor of a 1 7 form a gate 2 1 having a double-layered metal structure liquid crystal display and, more particularly, to a thin-film transistor having a gate including a double-layered metal 25 that provides double step difference between the doublelayered metal gate structure 2 1 and the substrate 11. The structure and a method of making such a double-layered formation of the gate 2 1 as described above and shown in metal gate. FIGS. 1A-1F requires the use of two photoresists 15,19 and 2. Discussion of Related Art two photoresist steps. An LCD (Liquid Crystal Display) includes a switching In the gate 21, shown in FIG. l C , the second metal layer device as a driving element, and a pixel-arranged matrix 30 1 7 is preferably centrally located on the first metal layer 13. structure having transparent or light-reflecting pixel elecAlthough there is no specific information available regardtrodes as its basic units. The switching device is a thin-film ing a relationship of w l to w2 of this related art method, transistor having gate, source and drain regions. based on their understanding of this related method resulting The gate of the thin-film transistor is made of aluminum in the structure shown in FIG. l C , the inventors of the to reduce its wiring resistance, but an aluminum gate may 35 invention described and claimed in the present application cause defects such as hillock. assume that the width difference wl-w2 between the first A double-layered metal gate, i.e., molybdenum-coated and second metal layers 13 and 17 is larger than or equal to aluminum gate is considered as a substitute for the alumi4 pm, that is, wl-w224 pm. num gate to overcome the problem of the hillock. Referring to FIG. ID, a first insulating layer 23 is formed 40 by depositing silicon oxide SiO, or silicon nitride Si,N, as To fabricate a double-layered gate, metals such as aluminum and molybdenum are sequentially deposited, followed a single-layered or double-layered structure on the gate 21 by a patterning process carried out via photolithography to and substrate 11. Semiconductor and ohmic contact layers form resulting metal films which have the same width. 25 and 27 are formed by sequentially depositing undoped Although the double-layered gate is desirable to overcome 45 polycrystalline silicon and heavily doped silicon on the first insulating layer 23. The semiconductor and ohmic contact the problem of hillock, the resulting deposited metal films layers 25 and 27 are patterned to expose the first insulating forming the double-layered gate are so thick that a severe layer 23 by photolithography. single step is created by a thickness difference between the metal films and a substrate, thereby causing a single step Referring to FIG. l E , conductive metal such as aluminum difference between the substrate and the double-layered gate is laminated on the insulating and ohmic contact layers 23 which deteriorates the step coverage of a later formed gate and 27. The conductive metal is patterned by photolithogoxide layer. The source and drain regions formed on the gate raphy so as to form source electrode 29 and a drain electrode oxide layer may have disconnections between areas of the 31. Aportion of the ohmic contact layer 27 exposed between source and drain regions which are overlapped and nonthe source and drain electrodes 29 and 31 is etched by using overlapped with the gate, or electrically exhibit short circuits 55 the source and drain electrodes 29 and 31 as masks. as a result of contact with the gate. Referrinn to FIG. IF. silicon oxide or silicon nitride is u According to another method of forming the gate, each of deposited on the entire surface of the structure to form a the metal layers of Al and Mo form a double step difference second insulating layer 33. The second insulating layer 33 is with the substrate so as to improve the step coverage of the etched to expose a designated portion of the drain electrode gate oxide layer. 60 31, thus forming a contact hole 35. By depositing transparent and conductive material on the second insulating layer FIGS. 1 A through 1 F are diagrams illustrating the process 33 and patterning it via photolithography, a pixel electrode for fabricating a thin-film transistor of a method which is 37 is formed so as to be electrically connected to the drain related to the invention described and claimed in the present electrode 31 through the contact hole 35. application. The method shown in FIGS. 1A-1F is not believed to be published prior art but is merely a recently 65 According to the method of fabricating a thin-film trandiscovered method related to the invention described and sistor as described above and shown in FIGS. 1A-IF, claimed in the present application. respective first and second metal layers are formed through
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photolithography using different masks so as to form the a substrate, depositing a second metal layer directly on the gate with a double-layered metal structure, resulting in first metal layer; forming a photoresist having a desired double step differences between the gate and substrate. width on the second metal layer; patterning the second metal layer via an isotropic etching using the photoresist as a As a result of the double step difference between the gate 1 2 1 and the substrate 1 shown in FIG. l C , a hillock often s mask; patterning the first metal layer via an anisotropic etching using the photoresist as a mask, the first metal layer occurs on both side portions of the first metal layer 13which being etched to have a desired width, thus forming a gate have no portion of the second metal layer 1 7 deposited having a laminated structure of the first and second layers; thereon when the first metal layer 13 is wider than the and removing the photoresist. second metal layer 1 7 as in FIG. 1C. Another problem with this related art method is that the process for forming a gate 10 These and other elements, features, and advantages of the is complex and requires two photoresists 15, 19 and two preferred embodiments of the present invention will be steps of deposition and photolithography. As a result, the apparent from the following detailed description of the contact resistance between the first and second metal layers preferred embodiments of the present invention, as illusmay be increased. trated in the accompanying drawings. Another related art method of forming a double metal 15 BRIEF DESCRIPTION OF THE DRAWINGS layer gate structure is described in "Low Cost, High Quality TFT-LCD Process", SOCIETY FOR INFORMATION DISThe accompanying drawings, which are included to proPLAY EURO DISPLAY 96, Proceedings of the 16th Intervide a further understanding of the invention and are incornational Display Research Conference, Birmingham, porated in and constitute a part of this specification, illustrate England, Oct. 1,1996, Pages 591-594. One Page 592 of this 20 preferred embodiments of the invention and together with publication, a method of forming a double metal gate the description serve to explain the principles of the structure includes the process of depositing two metal layers invention, in which: first and then patterning the layer FIGS, 1 A through 1 F are diagrams illustrating a process eliminate an additional photoresist step. However, with this for fabricating a thin-film transistor according to a method of method, process difficulties during the one step photoresist 25 the related art; process for forming the double metal layer gate resulted in FIG. 2 is a top view of a thin-film transistor according to the top layer being wider than the bottom layer causing an a preferred embodiment of the present invention; overhang condition in which the top layer overhangs the FIG. 3 is a cross-sectional view taken along line 111-111 bottom layer. This difficulty may result in poor step coverage 2; and and disconnection. This problem was solved by using a 30 FIGS. 4A through 4F are diagrams illustrating a process three-step etching process in which the photoresist had to be for fabricating a thin-film transistor of preferred embodibaked before each of the three etching steps to avoid lift-off ments of the present invention. or removal of the photoresist during etching. This three-step etching process and required bakng o f the DETAILED DESCRIPTION OF PREFERRED significantly increases the complexity and steps of the gate 35 EMBODIMENTS forming method. Reference will now be made in detail to preferred SUMMARY OF THE INVENTION embodiments of the present invention, examples of which are illustrated in the accompanying drawings. To overcome the problems discussed above, the preferred 40 embodiments of the present invention provide a thin-film FIG. 2 is a top view of a thin-film transistor according to transistor which prevents a hillock and deterioration of step a preferred embodiment of the present invention. FIG. 3 is coverage of a later formed gate oxide layer on a double a cross-sectional view taken along line 111-111 of FIG. 2. metal layer gate. The thin-film transistor comprises a gate 49 having a The preferred embodiments of the present invention also 45 double-layered structure of a first metal layer 43, a second provide a method of fabricating a thin-film transistor that metal layer 45 disposed on a substrate 41, a first insulating simplifies the process for forming a double metal layer gate. layer 51, a second insulating layers 61, a semiconductor layer 53, an ohmic contact layer 55, a source electrode 57, The preferred embodiments of the present invention fura drain electrode 59, and a pixel electrode 65. ther provide a method of fabricating a thin-film transistor that reduces the contact resistance between the first and The gate 49 has a double-layered structure including the second metal layers constituting a gate. first and second metal layers 43 and 45 disposed on the substrate 41. The first metal layer 43 is preferably formed Additional features and advantages of the invention will from a conductive metal such as Al, Cu, or Au deposited to be set forth in the description which follows, and in part will have a certain width w l . The second metal layer 45 is be apparent from the description, or may be learned by practice of the invention. The objectives and other advan- 5s preferably formed from a refractory metal such as Mo, Ta, or Co deposited to have a certain width w2. tages of the invention will be realized and attained by the structure particularly pointed out in the written description The present inventors have discovered that a relationship and claims hereof, as well as, the appended drawings. between the width of the first metal layer and the width of the second metal layer of a double metal layer gate electrode To achieve these and other advantages and in accordance with the purpose of the preferred embodiments of the 60 is critical to preventing deterioration of step coverage of a present invention, as embodied and broadly described, a later formed gate oxide layer in such a structure having a thin-film transistor preferably comprises a substrate, and a double step difference between the substrate and the gate. gate including a double-layered structure of first and second More specifically, the present inventors determined that a metal layers disposed on the substrate, the first metal layer structure wherein the first metal layer 43 is wider than the being wider than the second metal layer by about 1to 4 pm, 65 second metal layer 45 by about 1 to 4 pm, for example, 1 and a method of making such a thin-film transistor preferpmewl-w2e4 pm, provides maximum prevention of deteably comprises the steps of: depositing a first metal layer on rioration of step coverage of a later formed gate oxide layer
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in such a structure having a double step difference between respectively, by means of sputtering or chemical vapor deposition (hereinafter, referred to as CVD) without breakthe substrate and the gate. ing a vacuum state. As a result, the contact resistance To achieve the best results, the second metal layer 45 is between the first and second layers 43 and 45 is preferably positioned substantially in the middle of the first metal layer 45, so that both side portions of the first metal s According the preferred the present layer 43 which have no portion of the second metal layer 45 invention, a single photoresist step is used to pattern both the disposed thereon have the same width as each first layer 43 and the second layer 45 simultaother, The width of each of the side portions is preferably neously. In the single photoresist step, a photoresist 47 is larger than about 0.5 pm but less than about 2 pm. lo deposited on the second metal layer 45 and then the photoThe first layer s is preferably formed by ' resist 47 is patterned through exposure and development to depositing single layer of silicon oxide SiO, or silicon have the width wl on a designated portion of the second nitride Si3N4 on the substrate including the gate 49. metal layer 45. The semiconductor and ohmic contact layers 53 and 55 Referring to FIG, 4B, the second metal layer 45 is are formed on the portion of the first insulating layer 51 patterned with an etching solution preferably prepared with corresponding to the gate 49 by sequentially depositing a mixture of phosphoric acid H3P04, acetic acid CH,COOH u n d o ~ e damorphous silicon and heavily doped amorphous and nitric acid HNO,, by means of a wet etching using the silicon and patterning the two silicon layers. The semiconphotoresist 47 as a mask, Because the portion of the second ductor layer 53 is used as the active region of an element, metal layer 45 covered with the photoresist 47, as well as, thus forming a channel by means of a voltage applied to the exposed side portions of the second metal layer 45 are gate 49. The ohmic contact layer 55 provides an ohmic 20 isotropically etched, the second metal layer 45 is preferably contact between the semiconductor layer 53 and the source patterned to have the width w2 which is narrower than the and drain electrodes 57 and 59. The ohmic contact layer 55 width w l of the photoresist 47 which is the same as the is not formed in the portion that becomes the channel of the width w l of the first metal layer 43, that is, about 1 semiconductor layer 53. 2s pmewl-w2<4 pm. Each side portion of the second metal layer 45 preferably has a width larger than about 0.5 pm and The source and drain electrodes 57 and 59 are in contact less than about 2 pm. That is, the two side portions of the with the ohmic contact layer 55, and each electrode 57, 59 extends to a designated portion on the first insulating layer second metal layer 45 covered with the photoresist 47 are 51. preferably etched to have substantially the same width as The second insulating layer 61 is formed by depositing 30 each other. The lateral surfaces of the second metal layer 45 are preferably etched to have a substantially rectangular or insulating material such as silicon oxide SiO, silicon nitride inclined shape. Si3N4to cover the source and drain electrodes 57 and 59 and Referring to FIG. 4C, the first metal layer 43 is patterned the first insulating layer 51. The second insulating layer 61 via dry etching having anisotropic etching characteristic on the drain electrode 59 is removed to form a contact hole 63. The pixel electrode 65 is formed from transparent and 3s such as reactive ion etching (hereinafter, referred to as RIE) by using the photoresist 47 as a mask. When etching the first conductive material such as IT0 (Indium Tin Oxide) or Tin metal layer 43 other than the portion of the layer 43 covered oxide SnO,, so that it is connected to the drain electrode 59 with the photoresist 47, the first metal layer 43 preferably through the contact hole 63. has the same width w l of the photoresist 47. Thus, patternIn the first and second metal layers 43 and 45 constituting the gate 49, each side portion of the first metal layer 43 40 ing of the first and second metal layers 43,45, respectively, only requires two etching steps and does not require baking having no portion of the second metal layer 45 thereon has of the photoresist before each step of etching. Also, the a width that is preferably larger than about 0.5 pm and less relation between the first and second metal layers 43 and 45 than about 2 pm. Because the first metal layer 43 is wider also may be represented by about 1pm
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insulating layer 41 by CVD, thus forming semiconductor and ohmic contact layers 53 and 55. The ohmic contact and semiconductor lavers 55 and 53 are patterned bv means of photolithography~toexpose the first insulating layer 51. Referring to FIG. 4E, conductive metal such as Al or Cr is laminated on the insulating and ohmic contact layers 51 and 55 and patterned by photolithography to form source and drain electrodes 57 and 59. The ohmic contact layer 55 exposed between the source and drain electrodes 57 and 59 is etched by using the source drain electrodes 57 and 59 as masks. Referring to FIG. 4F, a second insulating layer 61 is formed by depositing insulating material such as silicon oxide or silicon nitride by CVD on the entire surface of the above structure. The second insulating layer is removed by photolithography to expose a designated portion of the drain electrode 59 and thus form a contact hole 63. Once transparent and conductive material such as I T 0 (Indium Tin Oxide) or Tin oxide SnO, is deposited on the second insulating layer 61 via sputtering and patterned by photolithography, a pixel electrode 65 is formed so that it is electrically connected to the drain electrode 59 through the contact hole 63. In another preferred embodiment of the present invention, the first and second metal layers 43 and 45 are first etched by means of a dry etching having anisotropic etching characteristic such as RIE by using the photoresist 47 as a mask. The gate 49 is formed by etching the second metal layer 45 under the photoresist 47 with an etching solution prepared with a mixture of phosphoric acid H3P04, acetic acid CH,COOH and nitric acid HNO,. In still another preferred embodiment of the present invention, the gate 49 is formed through a single etching step process for etching the first and second metal layers 43 and 45 simultaneously and via a single etching step, where the second metal layer 45 is etched more quickly than the first metal layer 43 with an etching solution prepared with a mixture of p ~ o s p ~ o r i c H,PO,, acetic acid CH,COOH acid and nitric acid HNO,. Because of the etching material and metals used for the first and second metal layers of the gate, only a single etching step is required. Despite the fact that a single etching step is used, it is still possible to obtain the relationship between the widths w l and w2 of the first and second metal layers described above. In this process, the first and second metal layers forming the gate 49 are formed and patterned with a single photo resist step as described above and a single etching step. As described above, in the preferred embodiments of the present invention, the first and second metal layers are sequentially deposited on the substrate without performing a masking step between the step of depositing the first metal layer and the second metal layer, followed by forming a photoresist that covers a designated portion of the second metal layer. In one preferred embodiment, the second metal layer is wet etched by using the photoresist as a mask but the first metal layer is dry etched. As a result, the double-metal gate is formed. In another preferred embodiment, a single etching step is used to form the double-metal gate wherein both the first metal layer and the second metal layer are wet etched, but the difference in etching rates of the first and second metal layers produces different etching affectswhich result in the desired double-step structure. While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
8
What is claimed is: 1. A method of making a thin-film transistor, comprising the steas of: depositing a first metal layer on a substrate; s depositing a second metal layer on the first metal layer without forming a photoresist on the first metal layer beforehand; forming a photoresist having a predetermined width on the second metal layer; lo anisotropically etching the first and second metal layers so such that the first metal layer and the second metal layer have the same width of the photoresist by using the photoresist as a mask, isotropically etching the second metal layer such that the IS second metal layer is narrower than the first metal layer by about 1pm to about 4 pm by using the photoresist as a mask, thus forming a gate having a double-layered structure including the first and second metal layers; and the photoresist. 20 2. The method of making a thin-film transistor as claimed in claim 1, further comprising the steps of: forming a first insulating layer on the substrate including the gate; 2s forming a semiconductor layer and an ohmic contact layer on a portion of the first insulating layer at a location corresponding to the gate; forming a source electrode and drain electrode extending onto the first insulating layer on two sides of the ohmic 30 contact layer, and removing a portion of the ohmic contact layer exposed between the source and drain electrodes; and forming a second insulating layer covering the semiconductor layer, the the drain 35 and the first insulating layer. 3. The method of making a thin-film transistor as claimed in claim 1, wherein the first metal layer includes Al,CU, or
4. The method of making a thin-fil
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